1 // SPDX-License-Identifier: GPL-2.0
15 /* EIC registers definition */
27  * The PMIC EIC controller only has one bank, and each bank now can contain
33 #define SPRD_PMIC_EIC_BIT(x)		((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1))
48  * struct sprd_pmic_eic - PMIC EIC controller
52  * @offset: the EIC controller's offset address of the PMIC.
53  * @reg: the array to cache the EIC registers.
54  * @buslock: for bus lock/sync and unlock.
55  * @irq: the interrupt number of the PMIC EIC conteroller.
73 	regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg,  in sprd_pmic_eic_update()
84 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);  in sprd_pmic_eic_read()
129 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value);  in sprd_pmic_eic_set_debounce()
135 	return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value);  in sprd_pmic_eic_set_debounce()
147 	return -ENOTSUPP;  in sprd_pmic_eic_set_config()
155 	pmic_eic->reg[REG_IE] = 0;  in sprd_pmic_eic_irq_mask()
156 	pmic_eic->reg[REG_TRIG] = 0;  in sprd_pmic_eic_irq_mask()
164 	pmic_eic->reg[REG_IE] = 1;  in sprd_pmic_eic_irq_unmask()
165 	pmic_eic->reg[REG_TRIG] = 1;  in sprd_pmic_eic_irq_unmask()
176 		pmic_eic->reg[REG_IEV] = 1;  in sprd_pmic_eic_irq_set_type()
179 		pmic_eic->reg[REG_IEV] = 0;  in sprd_pmic_eic_irq_set_type()
185 		 * Will set the trigger level according to current EIC level  in sprd_pmic_eic_irq_set_type()
190 		return -ENOTSUPP;  in sprd_pmic_eic_irq_set_type()
201 	mutex_lock(&pmic_eic->buslock);  in sprd_pmic_eic_bus_lock()
221 				     pmic_eic->reg[REG_IEV]);  in sprd_pmic_eic_bus_sync_unlock()
226 			     pmic_eic->reg[REG_IE]);  in sprd_pmic_eic_bus_sync_unlock()
227 	/* Generate trigger start pulse for debounce EIC */  in sprd_pmic_eic_bus_sync_unlock()
229 			     pmic_eic->reg[REG_TRIG]);  in sprd_pmic_eic_bus_sync_unlock()
231 	mutex_unlock(&pmic_eic->buslock);  in sprd_pmic_eic_bus_sync_unlock()
252 		dev_warn(chip->parent, "PMIC EIC level was changed.\n");  in sprd_pmic_eic_toggle_trigger()
259 	/* Generate trigger start pulse for debounce EIC */  in sprd_pmic_eic_toggle_trigger()
266 	struct gpio_chip *chip = &pmic_eic->chip;  in sprd_pmic_eic_irq_handler()
271 	ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS,  in sprd_pmic_eic_irq_handler()
278 	for_each_set_bit(n, &status, chip->ngpio) {  in sprd_pmic_eic_irq_handler()
282 		girq = irq_find_mapping(chip->irq.domain, n);  in sprd_pmic_eic_irq_handler()
286 		 * The PMIC EIC can only support level trigger, so we can  in sprd_pmic_eic_irq_handler()
301 	pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL);  in sprd_pmic_eic_probe()
303 		return -ENOMEM;  in sprd_pmic_eic_probe()
305 	mutex_init(&pmic_eic->buslock);  in sprd_pmic_eic_probe()
307 	pmic_eic->irq = platform_get_irq(pdev, 0);  in sprd_pmic_eic_probe()
308 	if (pmic_eic->irq < 0)  in sprd_pmic_eic_probe()
309 		return pmic_eic->irq;  in sprd_pmic_eic_probe()
311 	pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL);  in sprd_pmic_eic_probe()
312 	if (!pmic_eic->map)  in sprd_pmic_eic_probe()
313 		return -ENODEV;  in sprd_pmic_eic_probe()
315 	ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset);  in sprd_pmic_eic_probe()
317 		dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n");  in sprd_pmic_eic_probe()
321 	ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL,  in sprd_pmic_eic_probe()
324 					dev_name(&pdev->dev), pmic_eic);  in sprd_pmic_eic_probe()
326 		dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n");  in sprd_pmic_eic_probe()
330 	pmic_eic->chip.label = dev_name(&pdev->dev);  in sprd_pmic_eic_probe()
331 	pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR;  in sprd_pmic_eic_probe()
332 	pmic_eic->chip.base = -1;  in sprd_pmic_eic_probe()
333 	pmic_eic->chip.parent = &pdev->dev;  in sprd_pmic_eic_probe()
334 	pmic_eic->chip.of_node = pdev->dev.of_node;  in sprd_pmic_eic_probe()
335 	pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input;  in sprd_pmic_eic_probe()
336 	pmic_eic->chip.request = sprd_pmic_eic_request;  in sprd_pmic_eic_probe()
337 	pmic_eic->chip.free = sprd_pmic_eic_free;  in sprd_pmic_eic_probe()
338 	pmic_eic->chip.set_config = sprd_pmic_eic_set_config;  in sprd_pmic_eic_probe()
339 	pmic_eic->chip.set = sprd_pmic_eic_set;  in sprd_pmic_eic_probe()
340 	pmic_eic->chip.get = sprd_pmic_eic_get;  in sprd_pmic_eic_probe()
341 	pmic_eic->chip.can_sleep = true;  in sprd_pmic_eic_probe()
343 	pmic_eic->intc.name = dev_name(&pdev->dev);  in sprd_pmic_eic_probe()
344 	pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask;  in sprd_pmic_eic_probe()
345 	pmic_eic->intc.irq_unmask = sprd_pmic_eic_irq_unmask;  in sprd_pmic_eic_probe()
346 	pmic_eic->intc.irq_set_type = sprd_pmic_eic_irq_set_type;  in sprd_pmic_eic_probe()
347 	pmic_eic->intc.irq_bus_lock = sprd_pmic_eic_bus_lock;  in sprd_pmic_eic_probe()
348 	pmic_eic->intc.irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock;  in sprd_pmic_eic_probe()
349 	pmic_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;  in sprd_pmic_eic_probe()
351 	irq = &pmic_eic->chip.irq;  in sprd_pmic_eic_probe()
352 	irq->chip = &pmic_eic->intc;  in sprd_pmic_eic_probe()
353 	irq->threaded = true;  in sprd_pmic_eic_probe()
355 	ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic);  in sprd_pmic_eic_probe()
357 		dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);  in sprd_pmic_eic_probe()
366 	{ .compatible = "sprd,sc2731-eic", },
374 		.name = "sprd-pmic-eic",
381 MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver");