Lines Matching +full:display +full:- +full:hub
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
64 struct drm_device *drm = old_state->dev;
65 struct tegra_drm *tegra = drm->dev_private;
67 if (tegra->hub) {
91 return -ENOMEM;
93 idr_init_base(&fpriv->contexts, 1);
94 mutex_init(&fpriv->lock);
95 filp->driver_priv = fpriv;
102 context->client->ops->close_channel(context);
117 return &bo->base;
128 err = get_user(cmdbuf, &src->cmdbuf.handle);
132 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
136 err = get_user(target, &src->target.handle);
140 err = get_user(dest->target.offset, &src->target.offset);
144 err = get_user(dest->shift, &src->shift);
148 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
150 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
151 if (!dest->cmdbuf.bo)
152 return -ENOENT;
154 dest->target.bo = host1x_bo_lookup(file, target);
155 if (!dest->target.bo)
156 return -ENOENT;
165 struct host1x_client *client = &context->client->base;
166 unsigned int num_cmdbufs = args->num_cmdbufs;
167 unsigned int num_relocs = args->num_relocs;
172 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
179 user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
180 user_relocs = u64_to_user_ptr(args->relocs);
181 user_syncpt = u64_to_user_ptr(args->syncpts);
184 if (args->num_syncpts != 1)
185 return -EINVAL;
188 if (args->num_waitchks != 0)
189 return -EINVAL;
191 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
192 args->num_relocs);
194 return -ENOMEM;
196 job->num_relocs = args->num_relocs;
197 job->client = client;
198 job->class = client->class;
199 job->serialize = true;
209 err = -ENOMEM;
223 err = -EFAULT;
232 err = -EINVAL;
238 err = -ENOENT;
244 refs[num_refs++] = &obj->gem;
247 * Gather buffer base address must be 4-bytes aligned,
251 if (offset & 3 || offset > obj->gem.size) {
252 err = -EINVAL;
257 num_cmdbufs--;
262 while (num_relocs--) {
266 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
272 reloc = &job->relocs[num_relocs];
273 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
274 refs[num_refs++] = &obj->gem;
281 if (reloc->cmdbuf.offset & 3 ||
282 reloc->cmdbuf.offset >= obj->gem.size) {
283 err = -EINVAL;
287 obj = host1x_to_tegra_bo(reloc->target.bo);
288 refs[num_refs++] = &obj->gem;
290 if (reloc->target.offset >= obj->gem.size) {
291 err = -EINVAL;
297 err = -EFAULT;
304 err = -ENOENT;
308 job->is_addr_reg = context->client->ops->is_addr_reg;
309 job->is_valid_class = context->client->ops->is_valid_class;
310 job->syncpt_incrs = syncpt.incrs;
311 job->syncpt_id = syncpt.id;
312 job->timeout = 10000;
314 if (args->timeout && args->timeout < 10000)
315 job->timeout = args->timeout;
317 err = host1x_job_pin(job, context->client->base.dev);
327 args->fence = job->syncpt_end;
330 while (num_refs--)
348 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
349 &args->handle);
363 gem = drm_gem_object_lookup(file, args->handle);
365 return -EINVAL;
369 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
379 struct host1x *host = dev_get_drvdata(drm->dev->parent);
383 sp = host1x_syncpt_get(host, args->id);
385 return -EINVAL;
387 args->value = host1x_syncpt_read_min(sp);
394 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
398 sp = host1x_syncpt_get(host1x, args->id);
400 return -EINVAL;
408 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
412 sp = host1x_syncpt_get(host1x, args->id);
414 return -EINVAL;
416 return host1x_syncpt_wait(sp, args->thresh,
417 msecs_to_jiffies(args->timeout),
418 &args->value);
427 err = client->ops->open_channel(client, context);
431 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
433 client->ops->close_channel(context);
437 context->client = client;
438 context->id = err;
446 struct tegra_drm_file *fpriv = file->driver_priv;
447 struct tegra_drm *tegra = drm->dev_private;
451 int err = -ENODEV;
455 return -ENOMEM;
457 mutex_lock(&fpriv->lock);
459 list_for_each_entry(client, &tegra->clients, list)
460 if (client->base.class == args->client) {
465 args->context = context->id;
472 mutex_unlock(&fpriv->lock);
479 struct tegra_drm_file *fpriv = file->driver_priv;
484 mutex_lock(&fpriv->lock);
486 context = idr_find(&fpriv->contexts, args->context);
488 err = -EINVAL;
492 idr_remove(&fpriv->contexts, context->id);
496 mutex_unlock(&fpriv->lock);
503 struct tegra_drm_file *fpriv = file->driver_priv;
509 mutex_lock(&fpriv->lock);
511 context = idr_find(&fpriv->contexts, args->context);
513 err = -ENODEV;
517 if (args->index >= context->client->base.num_syncpts) {
518 err = -EINVAL;
522 syncpt = context->client->base.syncpts[args->index];
523 args->id = host1x_syncpt_id(syncpt);
526 mutex_unlock(&fpriv->lock);
533 struct tegra_drm_file *fpriv = file->driver_priv;
538 mutex_lock(&fpriv->lock);
540 context = idr_find(&fpriv->contexts, args->context);
542 err = -ENODEV;
546 err = context->client->ops->submit(context, args, drm, file);
549 mutex_unlock(&fpriv->lock);
556 struct tegra_drm_file *fpriv = file->driver_priv;
563 mutex_lock(&fpriv->lock);
565 context = idr_find(&fpriv->contexts, args->context);
567 err = -ENODEV;
571 if (args->syncpt >= context->client->base.num_syncpts) {
572 err = -EINVAL;
576 syncpt = context->client->base.syncpts[args->syncpt];
580 err = -ENXIO;
584 args->id = host1x_syncpt_base_id(base);
587 mutex_unlock(&fpriv->lock);
600 switch (args->mode) {
604 if (args->value != 0)
605 return -EINVAL;
612 if (args->value != 0)
613 return -EINVAL;
620 if (args->value > 5)
621 return -EINVAL;
623 value = args->value;
627 return -EINVAL;
630 gem = drm_gem_object_lookup(file, args->handle);
632 return -ENOENT;
636 bo->tiling.mode = mode;
637 bo->tiling.value = value;
652 gem = drm_gem_object_lookup(file, args->handle);
654 return -ENOENT;
658 switch (bo->tiling.mode) {
660 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
661 args->value = 0;
665 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
666 args->value = 0;
670 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
671 args->value = bo->tiling.value;
675 err = -EINVAL;
691 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
692 return -EINVAL;
694 gem = drm_gem_object_lookup(file, args->handle);
696 return -ENOENT;
699 bo->flags = 0;
701 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
702 bo->flags |= TEGRA_BO_BOTTOM_UP;
716 gem = drm_gem_object_lookup(file, args->handle);
718 return -ENOENT;
721 args->flags = 0;
723 if (bo->flags & TEGRA_BO_BOTTOM_UP)
724 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
788 struct tegra_drm_file *fpriv = file->driver_priv;
790 mutex_lock(&fpriv->lock);
791 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
792 mutex_unlock(&fpriv->lock);
794 idr_destroy(&fpriv->contexts);
795 mutex_destroy(&fpriv->lock);
802 struct drm_info_node *node = (struct drm_info_node *)s->private;
803 struct drm_device *drm = node->minor->dev;
806 mutex_lock(&drm->mode_config.fb_lock);
808 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
810 fb->base.id, fb->width, fb->height,
811 fb->format->depth,
812 fb->format->cpp[0] * 8,
816 mutex_unlock(&drm->mode_config.fb_lock);
823 struct drm_info_node *node = (struct drm_info_node *)s->private;
824 struct drm_device *drm = node->minor->dev;
825 struct tegra_drm *tegra = drm->dev_private;
828 if (tegra->domain) {
829 mutex_lock(&tegra->mm_lock);
830 drm_mm_print(&tegra->mm, &p);
831 mutex_unlock(&tegra->mm_lock);
846 minor->debugfs_root, minor);
886 mutex_lock(&tegra->clients_lock);
887 list_add_tail(&client->list, &tegra->clients);
888 client->drm = tegra;
889 mutex_unlock(&tegra->clients_lock);
897 mutex_lock(&tegra->clients_lock);
898 list_del_init(&client->list);
899 client->drm = NULL;
900 mutex_unlock(&tegra->clients_lock);
907 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
908 struct drm_device *drm = dev_get_drvdata(client->host);
909 struct tegra_drm *tegra = drm->dev_private;
916 * domain. This allows using the IOMMU-backed DMA API.
918 if (domain && domain != tegra->domain)
921 if (tegra->domain) {
922 group = iommu_group_get(client->dev);
924 return -ENODEV;
926 if (domain != tegra->domain) {
927 err = iommu_attach_group(tegra->domain, group);
934 tegra->use_explicit_iommu = true;
937 client->group = group;
944 struct drm_device *drm = dev_get_drvdata(client->host);
945 struct tegra_drm *tegra = drm->dev_private;
948 if (client->group) {
954 domain = iommu_get_domain_for_dev(client->dev);
956 iommu_detach_group(tegra->domain, client->group);
958 iommu_group_put(client->group);
959 client->group = NULL;
970 if (tegra->domain)
971 size = iova_align(&tegra->carveout.domain, size);
976 if (!tegra->domain) {
978 * Many units only support 32-bit addresses, even on 64-bit
979 * SoCs. If there is no IOMMU to translate into a 32-bit IO
981 * lower 32-bit range.
988 return ERR_PTR(-ENOMEM);
990 if (!tegra->domain) {
999 alloc = alloc_iova(&tegra->carveout.domain,
1000 size >> tegra->carveout.shift,
1001 tegra->carveout.limit, true);
1003 err = -EBUSY;
1007 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1008 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1016 __free_iova(&tegra->carveout.domain, alloc);
1026 if (tegra->domain)
1027 size = iova_align(&tegra->carveout.domain, size);
1031 if (tegra->domain) {
1032 iommu_unmap(tegra->domain, dma, size);
1033 free_iova(&tegra->carveout.domain,
1034 iova_pfn(&tegra->carveout.domain, dma));
1042 struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1051 * likely to be allocated beyond the 32-bit boundary if sufficient
1056 * 32-bit boundary.
1076 domain = iommu_get_domain_for_dev(dev->dev.parent);
1080 * 32-bit boundary, so the regular GATHER opcodes will always be
1097 drm = drm_dev_alloc(driver, &dev->dev);
1103 err = -ENOMEM;
1108 tegra->domain = iommu_domain_alloc(&platform_bus_type);
1109 if (!tegra->domain) {
1110 err = -ENOMEM;
1119 mutex_init(&tegra->clients_lock);
1120 INIT_LIST_HEAD(&tegra->clients);
1122 dev_set_drvdata(&dev->dev, drm);
1123 drm->dev_private = tegra;
1124 tegra->drm = drm;
1128 drm->mode_config.min_width = 0;
1129 drm->mode_config.min_height = 0;
1131 drm->mode_config.max_width = 4096;
1132 drm->mode_config.max_height = 4096;
1134 drm->mode_config.normalize_zpos = true;
1136 drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1137 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1149 if (tegra->use_explicit_iommu) {
1151 u64 dma_mask = dma_get_mask(&dev->dev);
1155 start = tegra->domain->geometry.aperture_start & dma_mask;
1156 end = tegra->domain->geometry.aperture_end & dma_mask;
1159 gem_end = end - CARVEOUT_SZ;
1163 order = __ffs(tegra->domain->pgsize_bitmap);
1164 init_iova_domain(&tegra->carveout.domain, 1UL << order,
1167 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1168 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1170 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1171 mutex_init(&tegra->mm_lock);
1174 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end);
1175 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start,
1177 } else if (tegra->domain) {
1178 iommu_domain_free(tegra->domain);
1179 tegra->domain = NULL;
1183 if (tegra->hub) {
1184 err = tegra_display_hub_prepare(tegra->hub);
1194 drm->irq_enabled = true;
1196 /* syncpoints are used for full 32-bit hardware VBLANK counters */
1197 drm->max_vblank_count = 0xffffffff;
1199 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1201 goto hub;
1208 goto hub;
1212 goto hub;
1222 hub:
1223 if (tegra->hub)
1224 tegra_display_hub_cleanup(tegra->hub);
1226 if (tegra->domain) {
1227 mutex_destroy(&tegra->mm_lock);
1228 drm_mm_takedown(&tegra->mm);
1229 put_iova_domain(&tegra->carveout.domain);
1240 if (tegra->domain)
1241 iommu_domain_free(tegra->domain);
1251 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1252 struct tegra_drm *tegra = drm->dev_private;
1262 if (tegra->hub)
1263 tegra_display_hub_cleanup(tegra->hub);
1267 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1269 if (tegra->domain) {
1270 mutex_destroy(&tegra->mm_lock);
1271 drm_mm_takedown(&tegra->mm);
1272 put_iova_domain(&tegra->carveout.domain);
1274 iommu_domain_free(tegra->domain);
1303 { .compatible = "nvidia,tegra20-dc", },
1304 { .compatible = "nvidia,tegra20-hdmi", },
1305 { .compatible = "nvidia,tegra20-gr2d", },
1306 { .compatible = "nvidia,tegra20-gr3d", },
1307 { .compatible = "nvidia,tegra30-dc", },
1308 { .compatible = "nvidia,tegra30-hdmi", },
1309 { .compatible = "nvidia,tegra30-gr2d", },
1310 { .compatible = "nvidia,tegra30-gr3d", },
1311 { .compatible = "nvidia,tegra114-dsi", },
1312 { .compatible = "nvidia,tegra114-hdmi", },
1313 { .compatible = "nvidia,tegra114-gr3d", },
1314 { .compatible = "nvidia,tegra124-dc", },
1315 { .compatible = "nvidia,tegra124-sor", },
1316 { .compatible = "nvidia,tegra124-hdmi", },
1317 { .compatible = "nvidia,tegra124-dsi", },
1318 { .compatible = "nvidia,tegra124-vic", },
1319 { .compatible = "nvidia,tegra132-dsi", },
1320 { .compatible = "nvidia,tegra210-dc", },
1321 { .compatible = "nvidia,tegra210-dsi", },
1322 { .compatible = "nvidia,tegra210-sor", },
1323 { .compatible = "nvidia,tegra210-sor1", },
1324 { .compatible = "nvidia,tegra210-vic", },
1325 { .compatible = "nvidia,tegra186-display", },
1326 { .compatible = "nvidia,tegra186-dc", },
1327 { .compatible = "nvidia,tegra186-sor", },
1328 { .compatible = "nvidia,tegra186-sor1", },
1329 { .compatible = "nvidia,tegra186-vic", },
1330 { .compatible = "nvidia,tegra194-display", },
1331 { .compatible = "nvidia,tegra194-dc", },
1332 { .compatible = "nvidia,tegra194-sor", },
1333 { .compatible = "nvidia,tegra194-vic", },
1386 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");