Lines Matching full:adc
3 * This file is part of STM32 ADC driver
29 #include "stm32-adc-core.h"
34 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
81 * struct stm32_adc_trig_info - ADC trigger info
91 * struct stm32_adc_calib - optional adc calibration data
105 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
158 * @smp_cycles: programmable sampling time (ADC clock cycles)
175 * struct stm32_adc - private data of each ADC IIO instance
176 * @common: reference to ADC block common data
177 * @offset: ADC instance register offset in ADC block
181 * @clk: clock for this adc instance
182 * @irq: interrupt for this adc instance
228 * struct stm32_adc_info - stm32 ADC, per instance config data
338 /* STM32F4 programmable sampling time (ADC clock cycles) */
432 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
453 * STM32 ADC registers access routines
454 * @adc: stm32 adc instance
455 * @reg: reg offset in adc instance
460 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) in stm32_adc_readl() argument
462 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
465 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
471 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) in stm32_adc_readw() argument
473 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
476 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) in stm32_adc_writel() argument
478 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
481 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_set_bits() argument
485 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
486 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); in stm32_adc_set_bits()
487 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
490 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) in stm32_adc_clr_bits() argument
494 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
495 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); in stm32_adc_clr_bits()
496 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
501 * @adc: stm32 adc instance
503 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) in stm32_adc_conv_irq_enable() argument
505 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
506 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
511 * @adc: stm32 adc instance
513 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) in stm32_adc_conv_irq_disable() argument
515 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
516 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
519 static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) in stm32_adc_ovr_irq_enable() argument
521 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_enable()
522 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_enable()
525 static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) in stm32_adc_ovr_irq_disable() argument
527 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, in stm32_adc_ovr_irq_disable()
528 adc->cfg->regs->ier_ovr.mask); in stm32_adc_ovr_irq_disable()
531 static void stm32_adc_set_res(struct stm32_adc *adc) in stm32_adc_set_res() argument
533 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res()
536 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
537 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
538 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
544 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_stop() local
546 if (adc->cfg->unprepare) in stm32_adc_hw_stop()
547 adc->cfg->unprepare(indio_dev); in stm32_adc_hw_stop()
549 if (adc->clk) in stm32_adc_hw_stop()
550 clk_disable_unprepare(adc->clk); in stm32_adc_hw_stop()
558 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_hw_start() local
561 if (adc->clk) { in stm32_adc_hw_start()
562 ret = clk_prepare_enable(adc->clk); in stm32_adc_hw_start()
567 stm32_adc_set_res(adc); in stm32_adc_hw_start()
569 if (adc->cfg->prepare) { in stm32_adc_hw_start()
570 ret = adc->cfg->prepare(indio_dev); in stm32_adc_hw_start()
578 if (adc->clk) in stm32_adc_hw_start()
579 clk_disable_unprepare(adc->clk); in stm32_adc_hw_start()
591 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
596 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_start_conv() local
598 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_start_conv()
601 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_start_conv()
604 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); in stm32f4_adc_start_conv()
610 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) in stm32f4_adc_start_conv()
611 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); in stm32f4_adc_start_conv()
616 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_stop_conv() local
618 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); in stm32f4_adc_stop_conv()
619 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); in stm32f4_adc_stop_conv()
621 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); in stm32f4_adc_stop_conv()
622 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, in stm32f4_adc_stop_conv()
628 struct stm32_adc *adc = iio_priv(indio_dev); in stm32f4_adc_irq_clear() local
630 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32f4_adc_irq_clear()
635 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_start_conv() local
645 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
646 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); in stm32h7_adc_start_conv()
648 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); in stm32h7_adc_start_conv()
649 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
651 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); in stm32h7_adc_start_conv()
656 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_stop_conv() local
660 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); in stm32h7_adc_stop_conv()
668 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); in stm32h7_adc_stop_conv()
673 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_irq_clear() local
675 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); in stm32h7_adc_irq_clear()
680 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_exit_pwr_down() local
684 /* Exit deep power down, then enable ADC voltage regulator */ in stm32h7_adc_exit_pwr_down()
685 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
686 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); in stm32h7_adc_exit_pwr_down()
688 if (adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
689 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_exit_pwr_down()
692 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
701 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_exit_pwr_down()
708 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) in stm32h7_adc_enter_pwr_down() argument
710 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); in stm32h7_adc_enter_pwr_down()
712 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ in stm32h7_adc_enter_pwr_down()
713 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); in stm32h7_adc_enter_pwr_down()
718 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_enable() local
722 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); in stm32h7_adc_enable()
724 /* Poll for ADRDY to be set (after adc startup time) */ in stm32h7_adc_enable()
729 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_enable()
730 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
733 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); in stm32h7_adc_enable()
741 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_disable() local
745 /* Disable ADC and wait until it's effectively disabled */ in stm32h7_adc_disable()
746 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); in stm32h7_adc_disable()
757 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
761 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_read_selfcalib() local
769 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_read_selfcalib()
780 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_read_selfcalib()
781 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
782 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
788 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT); in stm32h7_adc_read_selfcalib()
789 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); in stm32h7_adc_read_selfcalib()
790 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; in stm32h7_adc_read_selfcalib()
791 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); in stm32h7_adc_read_selfcalib()
792 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; in stm32h7_adc_read_selfcalib()
793 adc->cal.calibrated = true; in stm32h7_adc_read_selfcalib()
801 * Note: ADC must be enabled, with no on-going conversions.
805 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_restore_selfcalib() local
809 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | in stm32h7_adc_restore_selfcalib()
810 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); in stm32h7_adc_restore_selfcalib()
811 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val); in stm32h7_adc_restore_selfcalib()
820 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
821 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); in stm32h7_adc_restore_selfcalib()
822 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
838 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); in stm32h7_adc_restore_selfcalib()
846 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); in stm32h7_adc_restore_selfcalib()
847 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
859 * Fixed timeout value for ADC calibration.
864 * - 131,072 ADC clock cycle for the linear calibration
865 * - 20 ADC clock cycle for the offset calibration
872 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
874 * Note: Must be called once ADC is out of power down.
878 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_selfcalib() local
882 if (adc->cal.calibrated) in stm32h7_adc_selfcalib()
890 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF); in stm32h7_adc_selfcalib()
891 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN); in stm32h7_adc_selfcalib()
894 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
909 stm32_adc_set_bits(adc, STM32H7_ADC_CR, in stm32h7_adc_selfcalib()
911 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); in stm32h7_adc_selfcalib()
921 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, in stm32h7_adc_selfcalib()
928 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
931 * Configure channels as single ended or differential before enabling ADC.
932 * Enable ADC.
940 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_prepare() local
952 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); in stm32h7_adc_prepare()
966 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
973 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_prepare()
980 struct stm32_adc *adc = iio_priv(indio_dev); in stm32h7_adc_unprepare() local
982 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); in stm32h7_adc_unprepare()
984 stm32h7_adc_enter_pwr_down(adc); in stm32h7_adc_unprepare()
994 * Configure ADC scan sequence based on selected channels in scan_mask.
1001 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_conf_scan_seq() local
1002 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
1008 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
1009 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
1024 val = stm32_adc_readl(adc, sqr[i].reg); in stm32_adc_conf_scan_seq()
1027 stm32_adc_writel(adc, sqr[i].reg, val); in stm32_adc_conf_scan_seq()
1034 val = stm32_adc_readl(adc, sqr[0].reg); in stm32_adc_conf_scan_seq()
1037 stm32_adc_writel(adc, sqr[0].reg, val); in stm32_adc_conf_scan_seq()
1052 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_extsel() local
1056 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
1063 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
1064 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
1083 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig() local
1095 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1098 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1099 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1100 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1101 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1102 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1103 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1104 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1113 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_trig_pol() local
1115 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1123 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_get_trig_pol() local
1125 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1155 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_single_conv() local
1157 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1162 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1164 adc->bufi = 0; in stm32_adc_single_conv()
1173 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1174 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1177 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1180 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1183 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1186 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1188 stm32_adc_conv_irq_enable(adc); in stm32_adc_single_conv()
1190 adc->cfg->start_conv(indio_dev, false); in stm32_adc_single_conv()
1193 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1199 *res = adc->buffer[0]; in stm32_adc_single_conv()
1203 adc->cfg->stop_conv(indio_dev); in stm32_adc_single_conv()
1205 stm32_adc_conv_irq_disable(adc); in stm32_adc_single_conv()
1217 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_read_raw() local
1234 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1237 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1257 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_irq_clear() local
1259 adc->cfg->irq_clear(indio_dev, msk); in stm32_adc_irq_clear()
1265 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_threaded_isr() local
1266 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_threaded_isr()
1267 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_threaded_isr()
1273 * This requires to stop ADC first. OVR bit state in ISR, in stm32_adc_threaded_isr()
1276 adc->cfg->stop_conv(indio_dev); in stm32_adc_threaded_isr()
1288 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_isr() local
1289 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1290 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1300 stm32_adc_ovr_irq_disable(adc); in stm32_adc_isr()
1301 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1307 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1309 adc->bufi++; in stm32_adc_isr()
1310 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1311 stm32_adc_conv_irq_disable(adc); in stm32_adc_isr()
1315 complete(&adc->completion); in stm32_adc_isr()
1324 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1328 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1339 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_set_watermark() local
1350 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1358 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_update_scan_mode() local
1368 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); in stm32_adc_update_scan_mode()
1396 * To read a value from an ADC register:
1397 * echo [ADC reg offset] > direct_reg_access
1400 * To write a value in a ADC register:
1407 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_debugfs_reg_access() local
1418 stm32_adc_writel(adc, reg, writeval); in stm32_adc_debugfs_reg_access()
1420 *readval = stm32_adc_readl(adc, reg); in stm32_adc_debugfs_reg_access()
1437 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) in stm32_adc_dma_residue() argument
1442 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1443 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1447 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1451 if (i >= adc->bufi) in stm32_adc_dma_residue()
1452 size = i - adc->bufi; in stm32_adc_dma_residue()
1454 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1465 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_buffer_done() local
1466 int residue = stm32_adc_dma_residue(adc); in stm32_adc_dma_buffer_done()
1477 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1480 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1485 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1486 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1487 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1493 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_start() local
1498 if (!adc->dma_chan) in stm32_adc_dma_start()
1502 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1505 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1506 adc->rx_dma_buf, in stm32_adc_dma_start()
1507 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1519 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1524 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1531 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_postenable() local
1553 /* Reset adc buffer index */ in stm32_adc_buffer_postenable()
1554 adc->bufi = 0; in stm32_adc_buffer_postenable()
1556 stm32_adc_ovr_irq_enable(adc); in stm32_adc_buffer_postenable()
1558 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1559 stm32_adc_conv_irq_enable(adc); in stm32_adc_buffer_postenable()
1561 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1576 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_buffer_predisable() local
1579 adc->cfg->stop_conv(indio_dev); in stm32_adc_buffer_predisable()
1580 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1581 stm32_adc_conv_irq_disable(adc); in stm32_adc_buffer_predisable()
1583 stm32_adc_ovr_irq_disable(adc); in stm32_adc_buffer_predisable()
1585 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1586 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1606 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_trigger_handler() local
1608 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
1610 if (!adc->dma_chan) { in stm32_adc_trigger_handler()
1612 adc->bufi = 0; in stm32_adc_trigger_handler()
1613 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, in stm32_adc_trigger_handler()
1616 int residue = stm32_adc_dma_residue(adc); in stm32_adc_trigger_handler()
1619 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_trigger_handler()
1624 adc->bufi += indio_dev->scan_bytes; in stm32_adc_trigger_handler()
1625 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_trigger_handler()
1626 adc->bufi = 0; in stm32_adc_trigger_handler()
1633 if (!adc->dma_chan) in stm32_adc_trigger_handler()
1634 stm32_adc_conv_irq_enable(adc); in stm32_adc_trigger_handler()
1653 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_of_get_resolution() local
1658 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_of_get_resolution()
1660 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_of_get_resolution()
1661 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_of_get_resolution()
1663 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_of_get_resolution()
1669 adc->res = i; in stm32_adc_of_get_resolution()
1674 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) in stm32_adc_smpr_init() argument
1676 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
1680 /* Determine sampling time (ADC clock cycles) */ in stm32_adc_smpr_init()
1681 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
1683 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
1689 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
1696 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_init_one() local
1697 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
1715 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
1720 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1723 adc->difsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1725 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
1732 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_chan_of_init() local
1733 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_of_init()
1741 ret = of_property_count_u32_elems(node, "st,adc-channels"); in stm32_adc_chan_of_init()
1743 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_chan_of_init()
1749 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", in stm32_adc_chan_of_init()
1752 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_chan_of_init()
1759 ret = of_property_read_u32_array(node, "st,adc-diff-channels", in stm32_adc_chan_of_init()
1782 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { in stm32_adc_chan_of_init()
1824 stm32_adc_smpr_init(adc, channels[i].channel, smp); in stm32_adc_chan_of_init()
1835 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_dma_request() local
1839 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
1840 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
1841 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
1847 adc->dma_chan = NULL; in stm32_adc_dma_request()
1851 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
1853 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
1854 if (!adc->rx_buf) { in stm32_adc_dma_request()
1861 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
1862 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
1865 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
1872 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
1873 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
1875 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
1885 struct stm32_adc *adc; in stm32_adc_probe() local
1891 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
1895 adc = iio_priv(indio_dev); in stm32_adc_probe()
1896 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
1897 spin_lock_init(&adc->lock); in stm32_adc_probe()
1898 init_completion(&adc->completion); in stm32_adc_probe()
1899 adc->cfg = (const struct stm32_adc_cfg *) in stm32_adc_probe()
1909 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); in stm32_adc_probe()
1915 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
1916 if (adc->irq < 0) in stm32_adc_probe()
1917 return adc->irq; in stm32_adc_probe()
1919 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
1927 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
1928 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
1929 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
1930 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
1931 adc->clk = NULL; in stm32_adc_probe()
1950 if (!adc->dma_chan) in stm32_adc_probe()
1961 /* Get stm32-adc-core PM online */ in stm32_adc_probe()
1993 if (adc->dma_chan) { in stm32_adc_probe()
1994 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
1996 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
1997 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
2006 struct stm32_adc *adc = iio_priv(indio_dev); in stm32_adc_remove() local
2015 if (adc->dma_chan) { in stm32_adc_remove()
2016 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
2018 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
2019 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
2112 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2113 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2114 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2123 .name = "stm32-adc",
2131 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2133 MODULE_ALIAS("platform:stm32-adc");