Lines Matching full:dd
67 int hfi1_pcie_init(struct hfi1_devdata *dd) in hfi1_pcie_init() argument
70 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
86 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
92 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
105 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret); in hfi1_pcie_init()
113 dd_dev_err(dd, "Unable to set DMA consistent mask: %d\n", ret); in hfi1_pcie_init()
140 * Do remaining PCIe setup, once dd is allocated, and save away
144 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev) in hfi1_pcie_ddinit() argument
161 dd_dev_err(dd, "chip PIO range does not match\n"); in hfi1_pcie_ddinit()
165 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
166 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
167 dd_dev_err(dd, "UC mapping of kregbase1 failed\n"); in hfi1_pcie_ddinit()
170 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
173 dd->revision = readq(dd->kregbase1 + CCE_REVISION); in hfi1_pcie_ddinit()
174 if (dd->revision == ~(u64)0) { in hfi1_pcie_ddinit()
175 dd_dev_err(dd, "Cannot read chip CSRs\n"); in hfi1_pcie_ddinit()
179 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
180 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count); in hfi1_pcie_ddinit()
181 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; in hfi1_pcie_ddinit()
183 dd->kregbase2 = ioremap( in hfi1_pcie_ddinit()
184 addr + dd->base2_start, in hfi1_pcie_ddinit()
185 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
186 if (!dd->kregbase2) { in hfi1_pcie_ddinit()
187 dd_dev_err(dd, "UC mapping of kregbase2 failed\n"); in hfi1_pcie_ddinit()
190 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
191 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
193 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
194 if (!dd->piobase) { in hfi1_pcie_ddinit()
195 dd_dev_err(dd, "WC mapping of send buffers failed\n"); in hfi1_pcie_ddinit()
198 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
200 dd->physaddr = addr; /* used for io_remap, etc. */ in hfi1_pcie_ddinit()
206 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, in hfi1_pcie_ddinit()
208 if (!dd->rcvarray_wc) { in hfi1_pcie_ddinit()
209 dd_dev_err(dd, "WC mapping of receive array failed\n"); in hfi1_pcie_ddinit()
212 dd_dev_info(dd, "WC RcvArray: %p for %x\n", in hfi1_pcie_ddinit()
213 dd->rcvarray_wc, rcv_array_count * 8); in hfi1_pcie_ddinit()
215 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ in hfi1_pcie_ddinit()
219 hfi1_pcie_ddcleanup(dd); in hfi1_pcie_ddinit()
224 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
225 * to releasing the dd memory.
228 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd) in hfi1_pcie_ddcleanup() argument
230 dd->flags &= ~HFI1_PRESENT; in hfi1_pcie_ddcleanup()
231 if (dd->kregbase1) in hfi1_pcie_ddcleanup()
232 iounmap(dd->kregbase1); in hfi1_pcie_ddcleanup()
233 dd->kregbase1 = NULL; in hfi1_pcie_ddcleanup()
234 if (dd->kregbase2) in hfi1_pcie_ddcleanup()
235 iounmap(dd->kregbase2); in hfi1_pcie_ddcleanup()
236 dd->kregbase2 = NULL; in hfi1_pcie_ddcleanup()
237 if (dd->rcvarray_wc) in hfi1_pcie_ddcleanup()
238 iounmap(dd->rcvarray_wc); in hfi1_pcie_ddcleanup()
239 dd->rcvarray_wc = NULL; in hfi1_pcie_ddcleanup()
240 if (dd->piobase) in hfi1_pcie_ddcleanup()
241 iounmap(dd->piobase); in hfi1_pcie_ddcleanup()
242 dd->piobase = NULL; in hfi1_pcie_ddcleanup()
265 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
266 static void update_lbus_info(struct hfi1_devdata *dd) in update_lbus_info() argument
271 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in update_lbus_info()
273 dd_dev_err(dd, "Unable to read from PCI config\n"); in update_lbus_info()
277 dd->lbus_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat); in update_lbus_info()
278 dd->lbus_speed = extract_speed(linkstat); in update_lbus_info()
279 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in update_lbus_info()
280 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); in update_lbus_info()
287 int pcie_speeds(struct hfi1_devdata *dd) in pcie_speeds() argument
290 struct pci_dev *parent = dd->pcidev->bus->self; in pcie_speeds()
293 if (!pci_is_pcie(dd->pcidev)) { in pcie_speeds()
294 dd_dev_err(dd, "Can't find PCI Express capability!\n"); in pcie_speeds()
299 dd->link_gen3_capable = 1; in pcie_speeds()
301 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); in pcie_speeds()
303 dd_dev_err(dd, "Unable to read from PCI config\n"); in pcie_speeds()
308 dd_dev_info(dd, in pcie_speeds()
311 dd->link_gen3_capable = 0; in pcie_speeds()
318 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || in pcie_speeds()
319 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { in pcie_speeds()
320 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n"); in pcie_speeds()
321 dd->link_gen3_capable = 0; in pcie_speeds()
325 update_lbus_info(dd); in pcie_speeds()
327 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
337 int restore_pci_variables(struct hfi1_devdata *dd) in restore_pci_variables() argument
341 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); in restore_pci_variables()
345 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in restore_pci_variables()
346 dd->pcibar0); in restore_pci_variables()
350 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in restore_pci_variables()
351 dd->pcibar1); in restore_pci_variables()
355 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); in restore_pci_variables()
359 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, in restore_pci_variables()
360 dd->pcie_devctl); in restore_pci_variables()
364 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, in restore_pci_variables()
365 dd->pcie_lnkctl); in restore_pci_variables()
369 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, in restore_pci_variables()
370 dd->pcie_devctl2); in restore_pci_variables()
374 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); in restore_pci_variables()
378 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in restore_pci_variables()
379 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, in restore_pci_variables()
380 dd->pci_tph2); in restore_pci_variables()
387 dd_dev_err(dd, "Unable to write to PCI config\n"); in restore_pci_variables()
396 int save_pci_variables(struct hfi1_devdata *dd) in save_pci_variables() argument
400 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in save_pci_variables()
401 &dd->pcibar0); in save_pci_variables()
405 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in save_pci_variables()
406 &dd->pcibar1); in save_pci_variables()
410 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); in save_pci_variables()
414 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); in save_pci_variables()
418 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, in save_pci_variables()
419 &dd->pcie_devctl); in save_pci_variables()
423 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, in save_pci_variables()
424 &dd->pcie_lnkctl); in save_pci_variables()
428 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, in save_pci_variables()
429 &dd->pcie_devctl2); in save_pci_variables()
433 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); in save_pci_variables()
437 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in save_pci_variables()
438 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, in save_pci_variables()
439 &dd->pci_tph2); in save_pci_variables()
446 dd_dev_err(dd, "Unable to read from PCI config\n"); in save_pci_variables()
460 * @dd: Valid device data structure
463 void tune_pcie_caps(struct hfi1_devdata *dd) in tune_pcie_caps() argument
474 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); in tune_pcie_caps()
476 dd_dev_info(dd, "Enabling PCIe extended tags\n"); in tune_pcie_caps()
478 ret = pcie_capability_write_word(dd->pcidev, in tune_pcie_caps()
481 dd_dev_info(dd, "Unable to write to PCI config\n"); in tune_pcie_caps()
484 parent = dd->pcidev->bus->self; in tune_pcie_caps()
490 dd_dev_info(dd, "Parent not found\n"); in tune_pcie_caps()
494 dd_dev_info(dd, "Parent not root\n"); in tune_pcie_caps()
498 dd_dev_info(dd, "Parent is not PCI Express capable\n"); in tune_pcie_caps()
501 if (!pci_is_pcie(dd->pcidev)) { in tune_pcie_caps()
502 dd_dev_info(dd, "PCI device is not PCI Express capable\n"); in tune_pcie_caps()
508 ep_mpss = dd->pcidev->pcie_mpss; in tune_pcie_caps()
509 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in tune_pcie_caps()
526 pcie_set_mps(dd->pcidev, 128 << ep_mps); in tune_pcie_caps()
540 ep_mrrs = pcie_get_readrq(dd->pcidev); in tune_pcie_caps()
548 pcie_set_readrq(dd->pcidev, ep_mrrs); in tune_pcie_caps()
561 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_error_detected() local
566 dd_dev_info(dd, "State Normal, ignoring\n"); in pci_error_detected()
570 dd_dev_info(dd, "State Frozen, requesting reset\n"); in pci_error_detected()
576 if (dd) { in pci_error_detected()
577 dd_dev_info(dd, "State Permanent Failure, disabling\n"); in pci_error_detected()
579 dd->flags &= ~HFI1_PRESENT; in pci_error_detected()
580 hfi1_disable_after_error(dd); in pci_error_detected()
587 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n", in pci_error_detected()
598 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_mmio_enabled() local
601 if (dd && dd->pport) { in pci_mmio_enabled()
602 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); in pci_mmio_enabled()
605 dd_dev_info(dd, in pci_mmio_enabled()
615 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_slot_reset() local
617 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n"); in pci_slot_reset()
624 struct hfi1_devdata *dd = pci_get_drvdata(pdev); in pci_resume() local
626 dd_dev_info(dd, "HFI1 resume function called\n"); in pci_resume()
632 hfi1_init(dd, 1); /* same as re-init after reset */ in pci_resume()
769 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, in load_eq_table() argument
772 struct pci_dev *pdev = dd->pcidev; in load_eq_table()
789 ret = pci_read_config_dword(dd->pcidev, in load_eq_table()
792 dd_dev_err(dd, "Unable to read from PCI config\n"); in load_eq_table()
800 dd_dev_err(dd, in load_eq_table()
802 dd_dev_err(dd, " prec attn post\n"); in load_eq_table()
804 dd_dev_err(dd, " p%02d: %02x %02x %02x\n", in load_eq_table()
807 dd_dev_err(dd, " %02x %02x %02x\n", in load_eq_table()
822 static void pcie_post_steps(struct hfi1_devdata *dd) in pcie_post_steps() argument
826 set_sbus_fast_mode(dd); in pcie_post_steps()
835 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], in pcie_post_steps()
839 clear_sbus_fast_mode(dd); in pcie_post_steps()
848 static int trigger_sbr(struct hfi1_devdata *dd) in trigger_sbr() argument
850 struct pci_dev *dev = dd->pcidev; in trigger_sbr()
855 dd_dev_err(dd, "%s: no parent device\n", __func__); in trigger_sbr()
862 dd_dev_err(dd, in trigger_sbr()
879 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index, in write_gasket_interrupt() argument
882 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), in write_gasket_interrupt()
890 static void arm_gasket_logic(struct hfi1_devdata *dd) in arm_gasket_logic() argument
894 reg = (((u64)1 << dd->hfi1_id) << in arm_gasket_logic()
896 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << in arm_gasket_logic()
901 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); in arm_gasket_logic()
903 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); in arm_gasket_logic()
925 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname) in write_xmt_margin() argument
933 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL); in write_xmt_margin()
943 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ in write_xmt_margin()
957 if (is_ax(dd)) { in write_xmt_margin()
976 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); in write_xmt_margin()
979 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n", in write_xmt_margin()
986 int do_pcie_gen3_transition(struct hfi1_devdata *dd) in do_pcie_gen3_transition() argument
988 struct pci_dev *parent = dd->pcidev->bus->self; in do_pcie_gen3_transition()
1008 if (dd->icode != ICODE_RTL_SILICON) in do_pcie_gen3_transition()
1022 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__); in do_pcie_gen3_transition()
1027 if (dd->lbus_speed == target_speed) { in do_pcie_gen3_transition()
1028 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__, in do_pcie_gen3_transition()
1040 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n", in do_pcie_gen3_transition()
1046 target_width = dd->lbus_width; in do_pcie_gen3_transition()
1056 if (pcie_target == 3 && !dd->link_gen3_capable) { in do_pcie_gen3_transition()
1057 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n"); in do_pcie_gen3_transition()
1063 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT); in do_pcie_gen3_transition()
1065 dd_dev_err(dd, "%s: unable to acquire SBus resource\n", in do_pcie_gen3_transition()
1071 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); in do_pcie_gen3_transition()
1073 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in do_pcie_gen3_transition()
1075 dd_dev_info(dd, "%s: Disabled therm polling\n", in do_pcie_gen3_transition()
1084 dd_dev_info(dd, "%s: downloading firmware\n", __func__); in do_pcie_gen3_transition()
1085 ret = load_pcie_firmware(dd); in do_pcie_gen3_transition()
1093 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__); in do_pcie_gen3_transition()
1103 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); in do_pcie_gen3_transition()
1114 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1124 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1134 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ in do_pcie_gen3_transition()
1155 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, in do_pcie_gen3_transition()
1160 ret = load_eq_table(dd, eq, fs, div); in do_pcie_gen3_transition()
1172 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", in do_pcie_gen3_transition()
1176 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); in do_pcie_gen3_transition()
1177 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, in do_pcie_gen3_transition()
1186 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__); in do_pcie_gen3_transition()
1187 pcie_post_steps(dd); in do_pcie_gen3_transition()
1193 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050); in do_pcie_gen3_transition()
1196 write_gasket_interrupt(dd, intnum++, 0x0026, in do_pcie_gen3_transition()
1202 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202); in do_pcie_gen3_transition()
1212 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc); in do_pcie_gen3_transition()
1213 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf); in do_pcie_gen3_transition()
1214 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf); in do_pcie_gen3_transition()
1215 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw); in do_pcie_gen3_transition()
1219 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000); in do_pcie_gen3_transition()
1224 write_xmt_margin(dd, __func__); in do_pcie_gen3_transition()
1230 dd_dev_info(dd, "%s: clearing ASPM\n", __func__); in do_pcie_gen3_transition()
1231 aspm_hw_disable_l1(dd); in do_pcie_gen3_transition()
1249 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__); in do_pcie_gen3_transition()
1252 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1257 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1263 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1268 dd_dev_err(dd, "Unable to write to PCI config\n"); in do_pcie_gen3_transition()
1273 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__); in do_pcie_gen3_transition()
1276 dd_dev_info(dd, "%s: setting target link speed\n", __func__); in do_pcie_gen3_transition()
1277 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); in do_pcie_gen3_transition()
1279 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1284 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1288 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__, in do_pcie_gen3_transition()
1290 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); in do_pcie_gen3_transition()
1292 dd_dev_err(dd, "Unable to write to PCI config\n"); in do_pcie_gen3_transition()
1299 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in do_pcie_gen3_transition()
1300 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ in do_pcie_gen3_transition()
1302 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); in do_pcie_gen3_transition()
1304 dd_dev_info(dd, "%s: arming gasket logic\n", __func__); in do_pcie_gen3_transition()
1305 arm_gasket_logic(dd); in do_pcie_gen3_transition()
1320 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__); in do_pcie_gen3_transition()
1321 ret = trigger_sbr(dd); in do_pcie_gen3_transition()
1328 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); in do_pcie_gen3_transition()
1330 dd_dev_info(dd, in do_pcie_gen3_transition()
1337 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__); in do_pcie_gen3_transition()
1344 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__); in do_pcie_gen3_transition()
1345 ret = restore_pci_variables(dd); in do_pcie_gen3_transition()
1347 dd_dev_err(dd, "%s: Could not restore PCI variables\n", in do_pcie_gen3_transition()
1354 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); in do_pcie_gen3_transition()
1366 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); in do_pcie_gen3_transition()
1367 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg); in do_pcie_gen3_transition()
1369 dd_dev_err(dd, "SBR failed - unable to read from device\n"); in do_pcie_gen3_transition()
1376 write_csr(dd, CCE_DC_CTRL, 0); in do_pcie_gen3_transition()
1379 setextled(dd, 0); in do_pcie_gen3_transition()
1382 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition()
1384 dd_dev_err(dd, "Unable to read from PCI config\n"); in do_pcie_gen3_transition()
1389 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1394 if ((status & (1 << dd->hfi1_id)) == 0) { in do_pcie_gen3_transition()
1395 dd_dev_err(dd, in do_pcie_gen3_transition()
1397 __func__, status, 1 << dd->hfi1_id); in do_pcie_gen3_transition()
1406 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err); in do_pcie_gen3_transition()
1412 update_lbus_info(dd); in do_pcie_gen3_transition()
1413 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__, in do_pcie_gen3_transition()
1414 dd->lbus_info); in do_pcie_gen3_transition()
1416 if (dd->lbus_speed != target_speed || in do_pcie_gen3_transition()
1417 dd->lbus_width < target_width) { /* not target */ in do_pcie_gen3_transition()
1420 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n", in do_pcie_gen3_transition()
1432 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in do_pcie_gen3_transition()
1434 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()
1437 release_chip_resource(dd, CR_SBUS); in do_pcie_gen3_transition()
1441 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n"); in do_pcie_gen3_transition()
1445 dd_dev_info(dd, "%s: done\n", __func__); in do_pcie_gen3_transition()