Lines Matching +full:fifo +full:- +full:width
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 #define ITE_DRIVER_NAME "ite-cir"
26 /* FIFO sizes */
64 /* duty cycle, 0-100 */
67 /* hw-specific operation function pointers; most of these must be
68 * called while holding the spin lock, except for the TX FIFO length
83 /* read bytes from RX FIFO; return read count */
86 /* enable tx FIFO space available interrupt */
89 /* disable tx FIFO space available interrupt */
92 /* get number of full TX FIFO slots */
95 /* put a byte to the TX FIFO */
137 /* low-speed carrier frequency limits (Hz) */
141 /* high-speed carrier frequency limits (Hz) */
153 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
158 * frequency A = (H - L) / (H + L). We can use this in order to honor the
159 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
194 * (EC - LPC I/O)
215 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
225 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */
233 #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */
234 #define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default
235 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
236 * 0x30 -> 25 */
238 #define IT87_FIFOCLR 0x80 /* FIFO clear bit */
241 #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */
242 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
247 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
250 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
251 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */
259 #define IT87_II_RXFO 0x06 /* receiver FIFO overrun */
290 #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */
291 #define IT85_C0RFSR 0x0b /* receiver FIFO status register */
300 #define IT85_FIFOCLR 0x02 /* FIFO clear bit */
301 #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */
302 #define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default
303 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
304 * 0x0c -> 25 */
311 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
317 #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */
332 #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */
333 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
348 #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */
351 #define IT85_RXFBC 0x3f /* receiver FIFO count mask */
352 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */
372 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
373 * selectable by a single bank-select bit that's mapped onto both banks. The
376 * reserved high-order bit are placed at the same offset in both banks in
391 #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */
393 #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */
431 * a specific firmware running on the IT8512's embedded micro-controller.
432 * In addition of the embedded micro-controller, the IT8512 chip contains a
435 * micro-controller. The CIR module is only accessible by the
436 * micro-controller.
438 * The battery-backed SRAM module is accessible by the host CPU and the
439 * micro-controller. So one of the MC's firmware role is to act as a bridge
443 * communication protocol is not, so it was reverse-engineered.
457 #define IT8709_RFSR 0x1f /* receiver FIFO status register */
458 #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */