Lines Matching +full:canfd +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2014 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
84 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
92 #define XCAN_BTR_TS1_MASK 0x0000000F /* Time segment 1 */
95 #define XCAN_BTR_TS1_MASK_CANFD 0x0000003F /* Time segment 1 */
135 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
141 #define XCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
148 #define XCAN_TIMEOUT (1 * HZ)
150 /* TX-FIFO-empty interrupt available */
181 * struct xcan_priv - This definition define CAN driver instance
218 .tseg1_min = 1,
220 .tseg2_min = 1,
223 .brp_min = 1,
225 .brp_inc = 1,
228 /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */
231 .tseg1_min = 1,
233 .tseg2_min = 1,
236 .brp_min = 1,
238 .brp_inc = 1,
241 /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
244 .tseg1_min = 1,
246 .tseg2_min = 1,
249 .brp_min = 1,
251 .brp_inc = 1,
254 /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */
257 .tseg1_min = 1,
259 .tseg2_min = 1,
262 .brp_min = 1,
264 .brp_inc = 1,
267 /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
270 .tseg1_min = 1,
272 .tseg2_min = 1,
275 .brp_min = 1,
277 .brp_inc = 1,
281 * xcan_write_reg_le - Write a value to the device register little endian
291 iowrite32(val, priv->reg_base + reg); in xcan_write_reg_le()
295 * xcan_read_reg_le - Read a value from the device register little endian
304 return ioread32(priv->reg_base + reg); in xcan_read_reg_le()
308 * xcan_write_reg_be - Write a value to the device register big endian
318 iowrite32be(val, priv->reg_base + reg); in xcan_write_reg_be()
322 * xcan_read_reg_be - Read a value from the device register big endian
331 return ioread32be(priv->reg_base + reg); in xcan_read_reg_be()
335 * xcan_rx_int_mask - Get the mask for the receive interrupt
343 * while the FIFO is non-empty, but CAN FD HW does not have it in xcan_rx_int_mask()
345 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_int_mask()
352 * set_reset_mode - Resets the CAN device mode
365 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in set_reset_mode()
368 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { in set_reset_mode()
371 return -ETIMEDOUT; in set_reset_mode()
377 priv->tx_head = 0; in set_reset_mode()
378 priv->tx_tail = 0; in set_reset_mode()
384 * xcan_set_bittiming - CAN set bit timing routine
393 struct can_bittiming *bt = &priv->can.bittiming; in xcan_set_bittiming()
394 struct can_bittiming *dbt = &priv->can.data_bittiming; in xcan_set_bittiming()
401 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_set_bittiming()
405 "BUG! Cannot set bittiming - CAN is not in config mode\n"); in xcan_set_bittiming()
406 return -EPERM; in xcan_set_bittiming()
410 btr0 = (bt->brp - 1); in xcan_set_bittiming()
412 /* Setting Time Segment 1 in BTR Register */ in xcan_set_bittiming()
413 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); in xcan_set_bittiming()
416 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
419 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
421 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); in xcan_set_bittiming()
422 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); in xcan_set_bittiming()
424 if (priv->devtype.cantype == XAXI_CANFD || in xcan_set_bittiming()
425 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_set_bittiming()
427 btr0 = dbt->brp - 1; in xcan_set_bittiming()
429 /* Setting Time Segment 1 in BTR Register */ in xcan_set_bittiming()
430 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; in xcan_set_bittiming()
433 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
436 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
438 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0); in xcan_set_bittiming()
439 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1); in xcan_set_bittiming()
443 priv->read_reg(priv, XCAN_BRPR_OFFSET), in xcan_set_bittiming()
444 priv->read_reg(priv, XCAN_BTR_OFFSET)); in xcan_set_bittiming()
450 * xcan_chip_start - This the drivers start routine
487 if (priv->devtype.flags & XCAN_FLAG_RXMNF) in xcan_chip_start()
490 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_chip_start()
493 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in xcan_chip_start()
499 * filtering default to non-receipt if all filters are disabled in xcan_chip_start()
501 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) in xcan_chip_start()
502 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); in xcan_chip_start()
504 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); in xcan_chip_start()
505 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); in xcan_chip_start()
508 priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_chip_start()
510 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_chip_start()
515 * xcan_do_set_mode - This sets the mode of the driver
538 ret = -EOPNOTSUPP; in xcan_do_set_mode()
546 * xcan_write_frame - Write a frame to HW
555 struct canfd_frame *cf = (struct canfd_frame *)skb->data; in xcan_write_frame()
560 if (cf->can_id & CAN_EFF_FLAG) { in xcan_write_frame()
562 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & in xcan_write_frame()
564 id |= (((cf->can_id & CAN_EFF_MASK) >> in xcan_write_frame()
565 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) << in xcan_write_frame()
568 /* The substibute remote TX request bit should be "1" in xcan_write_frame()
573 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
578 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & in xcan_write_frame()
581 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
586 dlc = can_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT; in xcan_write_frame()
588 if (cf->flags & CANFD_BRS) in xcan_write_frame()
593 if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_write_frame()
594 (priv->devtype.flags & XCAN_FLAG_TXFEMP)) in xcan_write_frame()
595 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max); in xcan_write_frame()
599 priv->tx_head++; in xcan_write_frame()
601 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); in xcan_write_frame()
605 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); in xcan_write_frame()
606 if (priv->devtype.cantype == XAXI_CANFD || in xcan_write_frame()
607 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_write_frame()
608 for (i = 0; i < cf->len; i += 4) { in xcan_write_frame()
611 priv->write_reg(priv, ramoff, in xcan_write_frame()
612 be32_to_cpup((__be32 *)(cf->data + i))); in xcan_write_frame()
616 if (cf->len > 0) in xcan_write_frame()
617 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); in xcan_write_frame()
618 if (cf->len > 4) in xcan_write_frame()
619 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); in xcan_write_frame()
621 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_write_frame()
622 priv->write_reg(priv, in xcan_write_frame()
628 priv->write_reg(priv, in xcan_write_frame()
630 data[1]); in xcan_write_frame()
636 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode)
640 * Return: 0 on success, -ENOSPC if FIFO is full.
648 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_start_xmit_fifo()
650 return -ENOSPC; in xcan_start_xmit_fifo()
652 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
656 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ in xcan_start_xmit_fifo()
657 if (priv->tx_max > 1) in xcan_start_xmit_fifo()
658 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); in xcan_start_xmit_fifo()
661 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) in xcan_start_xmit_fifo()
664 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
670 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode)
674 * Return: 0 on success, -ENOSPC if there is no space
681 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & in xcan_start_xmit_mailbox()
683 return -ENOSPC; in xcan_start_xmit_mailbox()
685 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
691 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); in xcan_start_xmit_mailbox()
695 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
701 * xcan_start_xmit - Starts the transmission
717 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) in xcan_start_xmit()
732 * xcan_rx - Is called from CAN isr to complete the received
740 * Return: 1 on success and 0 on failure.
745 struct net_device_stats *stats = &ndev->stats; in xcan_rx()
752 stats->rx_dropped++; in xcan_rx()
757 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcan_rx()
758 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> in xcan_rx()
762 cf->can_dlc = get_can_dlc(dlc); in xcan_rx()
767 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcan_rx()
768 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcan_rx()
770 cf->can_id |= CAN_EFF_FLAG; in xcan_rx()
772 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
775 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcan_rx()
778 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
782 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); in xcan_rx()
783 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); in xcan_rx()
785 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_rx()
787 if (cf->can_dlc > 0) in xcan_rx()
788 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); in xcan_rx()
789 if (cf->can_dlc > 4) in xcan_rx()
790 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); in xcan_rx()
793 stats->rx_bytes += cf->can_dlc; in xcan_rx()
794 stats->rx_packets++; in xcan_rx()
797 return 1; in xcan_rx()
801 * xcanfd_rx - Is called from CAN isr to complete the received
809 * Return: 1 on success and 0 on failure.
814 struct net_device_stats *stats = &ndev->stats; in xcanfd_rx()
819 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcanfd_rx()
820 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)); in xcanfd_rx()
827 stats->rx_dropped++; in xcanfd_rx()
831 /* Change Xilinx CANFD data length format to socketCAN data in xcanfd_rx()
835 cf->len = can_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
838 cf->len = get_can_dlc((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
844 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcanfd_rx()
845 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcanfd_rx()
847 cf->can_id |= CAN_EFF_FLAG; in xcanfd_rx()
849 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
852 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcanfd_rx()
856 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
861 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
864 data[0] = priv->read_reg(priv, dw_offset); in xcanfd_rx()
865 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
869 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
871 data[0] = priv->read_reg(priv, dw_offset + i); in xcanfd_rx()
872 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
875 stats->rx_bytes += cf->len; in xcanfd_rx()
876 stats->rx_packets++; in xcanfd_rx()
879 return 1; in xcanfd_rx()
883 * xcan_current_error_state - Get current error state from HW
896 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); in xcan_current_error_state()
907 * xcan_set_error_state - Set new CAN error state
920 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); in xcan_set_error_state()
926 /* non-ERROR states are handled elsewhere */ in xcan_set_error_state()
933 cf->data[6] = txerr; in xcan_set_error_state()
934 cf->data[7] = rxerr; in xcan_set_error_state()
939 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
942 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
949 enum can_state old_state = priv->can.state; in xcan_update_error_state_after_rxtx()
970 struct net_device_stats *stats = &ndev->stats; in xcan_update_error_state_after_rxtx()
972 stats->rx_packets++; in xcan_update_error_state_after_rxtx()
973 stats->rx_bytes += cf->can_dlc; in xcan_update_error_state_after_rxtx()
980 * xcan_err_interrupt - error frame Isr
991 struct net_device_stats *stats = &ndev->stats; in xcan_err_interrupt()
995 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); in xcan_err_interrupt()
996 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); in xcan_err_interrupt()
999 priv->can.state = CAN_STATE_BUS_OFF; in xcan_err_interrupt()
1000 priv->can.can_stats.bus_off++; in xcan_err_interrupt()
1001 /* Leave device in Config Mode in bus-off state */ in xcan_err_interrupt()
1002 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in xcan_err_interrupt()
1008 if (new_state != priv->can.state) in xcan_err_interrupt()
1014 priv->can.can_stats.arbitration_lost++; in xcan_err_interrupt()
1021 stats->rx_over_errors++; in xcan_err_interrupt()
1022 stats->rx_errors++; in xcan_err_interrupt()
1024 cf.data[1] |= CAN_ERR_CRTL_RX_OVERFLOW; in xcan_err_interrupt()
1029 stats->rx_dropped++; in xcan_err_interrupt()
1030 stats->rx_errors++; in xcan_err_interrupt()
1033 cf.data[1] |= CAN_ERR_CRTL_UNSPEC; in xcan_err_interrupt()
1040 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { in xcan_err_interrupt()
1047 stats->tx_errors++; in xcan_err_interrupt()
1056 stats->tx_errors++; in xcan_err_interrupt()
1065 stats->rx_errors++; in xcan_err_interrupt()
1074 stats->rx_errors++; in xcan_err_interrupt()
1083 stats->rx_errors++; in xcan_err_interrupt()
1089 priv->can.can_stats.bus_error++; in xcan_err_interrupt()
1097 skb_cf->can_id |= cf.can_id; in xcan_err_interrupt()
1098 memcpy(skb_cf->data, cf.data, CAN_ERR_DLC); in xcan_err_interrupt()
1099 stats->rx_packets++; in xcan_err_interrupt()
1100 stats->rx_bytes += CAN_ERR_DLC; in xcan_err_interrupt()
1106 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); in xcan_err_interrupt()
1110 * xcan_state_interrupt - It will check the state of the CAN device
1123 priv->can.state = CAN_STATE_SLEEPING; in xcan_state_interrupt()
1127 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_state_interrupt()
1131 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame
1140 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { in xcan_rx_fifo_get_next_frame()
1143 /* clear RXOK before the is-empty check so that any newly in xcan_rx_fifo_get_next_frame()
1146 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); in xcan_rx_fifo_get_next_frame()
1148 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); in xcan_rx_fifo_get_next_frame()
1151 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1157 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1159 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1168 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & in xcan_rx_fifo_get_next_frame()
1170 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1180 * xcan_rx_poll - Poll routine for rx packets (NAPI)
1191 struct net_device *ndev = napi->dev; in xcan_rx_poll()
1204 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_poll()
1206 priv->write_reg(priv, XCAN_FSR_OFFSET, in xcan_rx_poll()
1209 /* clear rx-not-empty (will actually clear only if in xcan_rx_poll()
1212 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_rx_poll()
1223 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_rx_poll()
1225 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_rx_poll()
1231 * xcan_tx_interrupt - Tx Done Isr
1238 struct net_device_stats *stats = &ndev->stats; in xcan_tx_interrupt()
1240 int frames_sent = 1; /* TXOK => at least 1 frame was sent */ in xcan_tx_interrupt()
1250 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_tx_interrupt()
1252 frames_in_fifo = priv->tx_head - priv->tx_tail; in xcan_tx_interrupt()
1256 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1257 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1261 /* Check if 2 frames were sent (TXOK only means that at least 1 in xcan_tx_interrupt()
1264 if (frames_in_fifo > 1) { in xcan_tx_interrupt()
1265 WARN_ON(frames_in_fifo > priv->tx_max); in xcan_tx_interrupt()
1268 * (1) isr variable is up-to-date at least up to TXOK clear in xcan_tx_interrupt()
1275 * clear to satisfy (1). in xcan_tx_interrupt()
1279 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_tx_interrupt()
1281 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_tx_interrupt()
1290 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1293 while (frames_sent--) { in xcan_tx_interrupt()
1294 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % in xcan_tx_interrupt()
1295 priv->tx_max); in xcan_tx_interrupt()
1296 priv->tx_tail++; in xcan_tx_interrupt()
1297 stats->tx_packets++; in xcan_tx_interrupt()
1302 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1309 * xcan_interrupt - CAN Isr
1317 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
1328 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_interrupt()
1334 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | in xcan_interrupt()
1348 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); in xcan_interrupt()
1354 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_interrupt()
1356 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_interrupt()
1357 napi_schedule(&priv->napi); in xcan_interrupt()
1363 * xcan_chip_stop - Driver stop routine
1379 priv->can.state = CAN_STATE_STOPPED; in xcan_chip_stop()
1383 * xcan_open - Driver open routine
1394 ret = pm_runtime_get_sync(priv->dev); in xcan_open()
1401 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, in xcan_open()
1402 ndev->name, ndev); in xcan_open()
1427 napi_enable(&priv->napi); in xcan_open()
1435 free_irq(ndev->irq, ndev); in xcan_open()
1437 pm_runtime_put(priv->dev); in xcan_open()
1443 * xcan_close - Driver close routine
1453 napi_disable(&priv->napi); in xcan_close()
1455 free_irq(ndev->irq, ndev); in xcan_close()
1459 pm_runtime_put(priv->dev); in xcan_close()
1465 * xcan_get_berr_counter - error counter routine
1478 ret = pm_runtime_get_sync(priv->dev); in xcan_get_berr_counter()
1482 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1486 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; in xcan_get_berr_counter()
1487 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & in xcan_get_berr_counter()
1490 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1503 * xcan_suspend - Suspend method for the driver
1523 * xcan_resume - Resume from suspend
1555 * xcan_runtime_suspend - Runtime suspend method for the driver
1566 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_suspend()
1567 clk_disable_unprepare(priv->can_clk); in xcan_runtime_suspend()
1573 * xcan_runtime_resume - Runtime resume from suspend
1585 ret = clk_prepare_enable(priv->bus_clk); in xcan_runtime_resume()
1590 ret = clk_prepare_enable(priv->can_clk); in xcan_runtime_resume()
1593 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_resume()
1649 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
1650 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data },
1651 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data },
1652 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data },
1658 * xcan_probe - Platform registration call
1685 of_id = of_match_device(xcan_of_match, &pdev->dev); in xcan_probe()
1686 if (of_id && of_id->data) in xcan_probe()
1687 devtype = of_id->data; in xcan_probe()
1689 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? in xcan_probe()
1690 "tx-mailbox-count" : "tx-fifo-depth"; in xcan_probe()
1692 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, in xcan_probe()
1695 dev_err(&pdev->dev, "missing %s property\n", in xcan_probe()
1700 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", in xcan_probe()
1703 dev_err(&pdev->dev, in xcan_probe()
1704 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); in xcan_probe()
1713 * to determine if 1 or 2 frames have been sent. in xcan_probe()
1718 * sent), which is not a sensible state - possibly TXFWMEMP is not in xcan_probe()
1726 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_probe()
1727 (devtype->flags & XCAN_FLAG_TXFEMP)) in xcan_probe()
1730 tx_max = 1; in xcan_probe()
1737 return -ENOMEM; in xcan_probe()
1740 priv->dev = &pdev->dev; in xcan_probe()
1741 priv->can.bittiming_const = devtype->bittiming_const; in xcan_probe()
1742 priv->can.do_set_mode = xcan_do_set_mode; in xcan_probe()
1743 priv->can.do_get_berr_counter = xcan_get_berr_counter; in xcan_probe()
1744 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in xcan_probe()
1747 if (devtype->cantype == XAXI_CANFD) in xcan_probe()
1748 priv->can.data_bittiming_const = in xcan_probe()
1751 if (devtype->cantype == XAXI_CANFD_2_0) in xcan_probe()
1752 priv->can.data_bittiming_const = in xcan_probe()
1755 if (devtype->cantype == XAXI_CANFD || in xcan_probe()
1756 devtype->cantype == XAXI_CANFD_2_0) in xcan_probe()
1757 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD; in xcan_probe()
1759 priv->reg_base = addr; in xcan_probe()
1760 priv->tx_max = tx_max; in xcan_probe()
1761 priv->devtype = *devtype; in xcan_probe()
1762 spin_lock_init(&priv->tx_lock); in xcan_probe()
1769 ndev->irq = ret; in xcan_probe()
1771 ndev->flags |= IFF_ECHO; /* We support local echo */ in xcan_probe()
1774 SET_NETDEV_DEV(ndev, &pdev->dev); in xcan_probe()
1775 ndev->netdev_ops = &xcan_netdev_ops; in xcan_probe()
1778 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); in xcan_probe()
1779 if (IS_ERR(priv->can_clk)) { in xcan_probe()
1780 if (PTR_ERR(priv->can_clk) != -EPROBE_DEFER) in xcan_probe()
1781 dev_err(&pdev->dev, "Device clock not found.\n"); in xcan_probe()
1782 ret = PTR_ERR(priv->can_clk); in xcan_probe()
1786 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); in xcan_probe()
1787 if (IS_ERR(priv->bus_clk)) { in xcan_probe()
1788 if (PTR_ERR(priv->bus_clk) != -EPROBE_DEFER) in xcan_probe()
1789 dev_err(&pdev->dev, "bus clock not found\n"); in xcan_probe()
1790 ret = PTR_ERR(priv->bus_clk); in xcan_probe()
1794 priv->write_reg = xcan_write_reg_le; in xcan_probe()
1795 priv->read_reg = xcan_read_reg_le; in xcan_probe()
1797 pm_runtime_enable(&pdev->dev); in xcan_probe()
1798 ret = pm_runtime_get_sync(&pdev->dev); in xcan_probe()
1805 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { in xcan_probe()
1806 priv->write_reg = xcan_write_reg_be; in xcan_probe()
1807 priv->read_reg = xcan_read_reg_be; in xcan_probe()
1810 priv->can.clock.freq = clk_get_rate(priv->can_clk); in xcan_probe()
1812 netif_napi_add(ndev, &priv->napi, xcan_rx_poll, rx_max); in xcan_probe()
1816 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); in xcan_probe()
1822 pm_runtime_put(&pdev->dev); in xcan_probe()
1824 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) { in xcan_probe()
1825 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000); in xcan_probe()
1826 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000); in xcan_probe()
1830 priv->reg_base, ndev->irq, priv->can.clock.freq, in xcan_probe()
1831 hw_tx_max, priv->tx_max); in xcan_probe()
1836 pm_runtime_put(priv->dev); in xcan_probe()
1837 pm_runtime_disable(&pdev->dev); in xcan_probe()
1845 * xcan_remove - Unregister the device after releasing the resources
1857 pm_runtime_disable(&pdev->dev); in xcan_remove()
1858 netif_napi_del(&priv->napi); in xcan_remove()