Lines Matching +full:xrx200 +full:- +full:net
1 // SPDX-License-Identifier: GPL-2.0
7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de>
45 #include <net/dsa.h>
46 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p))
134 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
152 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
154 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
280 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index
281 u16 table; // PCE_TBL_CTRL.ADDR = pData->table
316 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */
331 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */
344 return __raw_readl(priv->gswip + (offset * 4)); in gswip_switch_r()
349 __raw_writel(val, priv->gswip + (offset * 4)); in gswip_switch_w()
367 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, in gswip_switch_r_timeout()
373 return __raw_readl(priv->mdio + (offset * 4)); in gswip_mdio_r()
378 __raw_writel(val, priv->mdio + (offset * 4)); in gswip_mdio_w()
393 return __raw_readl(priv->mii + (offset * 4)); in gswip_mii_r()
398 __raw_writel(val, priv->mii + (offset * 4)); in gswip_mii_w()
415 if (!dsa_is_cpu_port(priv->ds, port)) in gswip_mii_mask_cfg()
439 while (likely(cnt--)) { in gswip_mdio_poll()
447 return -ETIMEDOUT; in gswip_mdio_poll()
452 struct gswip_priv *priv = bus->priv; in gswip_mdio_wr()
457 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_wr()
472 struct gswip_priv *priv = bus->priv; in gswip_mdio_rd()
477 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_rd()
488 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); in gswip_mdio_rd()
497 struct dsa_switch *ds = priv->ds; in gswip_mdio()
499 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); in gswip_mdio()
500 if (!ds->slave_mii_bus) in gswip_mdio()
501 return -ENOMEM; in gswip_mdio()
503 ds->slave_mii_bus->priv = priv; in gswip_mdio()
504 ds->slave_mii_bus->read = gswip_mdio_rd; in gswip_mdio()
505 ds->slave_mii_bus->write = gswip_mdio_wr; in gswip_mdio()
506 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; in gswip_mdio()
507 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", in gswip_mdio()
508 dev_name(priv->dev)); in gswip_mdio()
509 ds->slave_mii_bus->parent = priv->dev; in gswip_mdio()
510 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; in gswip_mdio()
512 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); in gswip_mdio()
521 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : in gswip_pce_table_entry_read()
529 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); in gswip_pce_table_entry_read()
532 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, in gswip_pce_table_entry_read()
540 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) in gswip_pce_table_entry_read()
541 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); in gswip_pce_table_entry_read()
543 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) in gswip_pce_table_entry_read()
544 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); in gswip_pce_table_entry_read()
546 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); in gswip_pce_table_entry_read()
550 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); in gswip_pce_table_entry_read()
551 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); in gswip_pce_table_entry_read()
552 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; in gswip_pce_table_entry_read()
563 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : in gswip_pce_table_entry_write()
571 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); in gswip_pce_table_entry_write()
574 tbl->table | addr_mode, in gswip_pce_table_entry_write()
577 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) in gswip_pce_table_entry_write()
578 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); in gswip_pce_table_entry_write()
580 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) in gswip_pce_table_entry_write()
581 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); in gswip_pce_table_entry_write()
585 tbl->table | addr_mode, in gswip_pce_table_entry_write()
588 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); in gswip_pce_table_entry_write()
593 if (tbl->type) in gswip_pce_table_entry_write()
595 if (tbl->valid) in gswip_pce_table_entry_write()
597 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; in gswip_pce_table_entry_write()
614 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_add_single_port_br()
615 unsigned int max_ports = priv->hw_info->max_ports; in gswip_add_single_port_br()
619 dev_err(priv->dev, "single port for %i supported\n", port); in gswip_add_single_port_br()
620 return -EIO; in gswip_add_single_port_br()
630 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); in gswip_add_single_port_br()
644 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_add_single_port_br()
654 struct gswip_priv *priv = ds->priv; in gswip_port_enable()
680 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; in gswip_port_enable()
691 struct gswip_priv *priv = ds->priv; in gswip_port_disable()
743 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_filtering()
747 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; in gswip_port_vlan_filtering()
752 if (!!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) in gswip_port_vlan_filtering()
753 return -EIO; in gswip_port_vlan_filtering()
783 struct gswip_priv *priv = ds->priv; in gswip_setup()
784 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_setup()
793 for (i = 0; i < priv->hw_info->max_ports; i++) { in gswip_setup()
810 dev_err(priv->dev, "writing PCE microcode failed, %i", err); in gswip_setup()
841 for (i = 0; i < priv->hw_info->max_ports; i++) in gswip_setup()
870 dev_err(priv->dev, "MAC flushing didn't finish\n"); in gswip_setup()
890 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_active_create()
891 int idx = -1; in gswip_vlan_active_create()
896 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_active_create()
897 if (!priv->vlans[i].bridge) { in gswip_vlan_active_create()
903 if (idx == -1) in gswip_vlan_active_create()
904 return -ENOSPC; in gswip_vlan_active_create()
906 if (fid == -1) in gswip_vlan_active_create()
917 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); in gswip_vlan_active_create()
921 priv->vlans[idx].bridge = bridge; in gswip_vlan_active_create()
922 priv->vlans[idx].vid = vid; in gswip_vlan_active_create()
923 priv->vlans[idx].fid = fid; in gswip_vlan_active_create()
938 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); in gswip_vlan_active_remove()
939 priv->vlans[idx].bridge = NULL; in gswip_vlan_active_remove()
948 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_add_unaware()
949 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_add_unaware()
951 int idx = -1; in gswip_vlan_add_unaware()
956 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_add_unaware()
957 if (priv->vlans[i].bridge == bridge) { in gswip_vlan_add_unaware()
966 if (idx == -1) { in gswip_vlan_add_unaware()
967 idx = gswip_vlan_active_create(priv, bridge, -1, 0); in gswip_vlan_add_unaware()
982 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", in gswip_vlan_add_unaware()
993 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_add_unaware()
1010 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_add_aware()
1011 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_add_aware()
1013 int idx = -1; in gswip_vlan_add_aware()
1014 int fid = -1; in gswip_vlan_add_aware()
1019 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_add_aware()
1020 if (priv->vlans[i].bridge == bridge) { in gswip_vlan_add_aware()
1021 if (fid != -1 && fid != priv->vlans[i].fid) in gswip_vlan_add_aware()
1022 dev_err(priv->dev, "one bridge with multiple flow ids\n"); in gswip_vlan_add_aware()
1023 fid = priv->vlans[i].fid; in gswip_vlan_add_aware()
1024 if (priv->vlans[i].vid == vid) { in gswip_vlan_add_aware()
1034 if (idx == -1) { in gswip_vlan_add_aware()
1050 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", in gswip_vlan_add_aware()
1067 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_add_aware()
1085 unsigned int max_ports = priv->hw_info->max_ports; in gswip_vlan_remove()
1086 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_vlan_remove()
1087 int idx = -1; in gswip_vlan_remove()
1092 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_vlan_remove()
1093 if (priv->vlans[i].bridge == bridge && in gswip_vlan_remove()
1094 (!vlan_aware || priv->vlans[i].vid == vid)) { in gswip_vlan_remove()
1100 if (idx == -1) { in gswip_vlan_remove()
1101 dev_err(priv->dev, "bridge to leave does not exists\n"); in gswip_vlan_remove()
1102 return -ENOENT; in gswip_vlan_remove()
1109 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); in gswip_vlan_remove()
1117 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); in gswip_vlan_remove()
1125 dev_err(priv->dev, "failed to write active VLAN: %d\n", in gswip_vlan_remove()
1141 struct gswip_priv *priv = ds->priv; in gswip_port_bridge_join()
1151 priv->port_vlan_filter &= ~BIT(port); in gswip_port_bridge_join()
1153 priv->port_vlan_filter |= BIT(port); in gswip_port_bridge_join()
1161 struct gswip_priv *priv = ds->priv; in gswip_port_bridge_leave()
1175 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_prepare()
1176 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; in gswip_port_vlan_prepare()
1177 unsigned int max_ports = priv->hw_info->max_ports; in gswip_port_vlan_prepare()
1184 return -EOPNOTSUPP; in gswip_port_vlan_prepare()
1186 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { in gswip_port_vlan_prepare()
1187 int idx = -1; in gswip_port_vlan_prepare()
1190 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_port_vlan_prepare()
1191 if (priv->vlans[i].bridge == bridge && in gswip_port_vlan_prepare()
1192 priv->vlans[i].vid == vid) { in gswip_port_vlan_prepare()
1202 if (idx == -1) { in gswip_port_vlan_prepare()
1204 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { in gswip_port_vlan_prepare()
1205 if (!priv->vlans[pos].bridge) { in gswip_port_vlan_prepare()
1212 if (idx == -1) in gswip_port_vlan_prepare()
1213 return -ENOSPC; in gswip_port_vlan_prepare()
1223 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_add()
1224 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; in gswip_port_vlan_add()
1225 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in gswip_port_vlan_add()
1226 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in gswip_port_vlan_add()
1237 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) in gswip_port_vlan_add()
1244 struct gswip_priv *priv = ds->priv; in gswip_port_vlan_del()
1245 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; in gswip_port_vlan_del()
1246 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in gswip_port_vlan_del()
1258 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { in gswip_port_vlan_del()
1269 struct gswip_priv *priv = ds->priv; in gswip_port_fast_age()
1280 dev_err(priv->dev, "failed to read mac bridge: %d\n", in gswip_port_fast_age()
1297 dev_err(priv->dev, "failed to write mac bridge: %d\n", in gswip_port_fast_age()
1306 struct gswip_priv *priv = ds->priv; in gswip_port_stp_state_set()
1325 dev_err(priv->dev, "invalid STP state: %d\n", state); in gswip_port_stp_state_set()
1338 struct gswip_priv *priv = ds->priv; in gswip_port_fdb()
1339 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; in gswip_port_fdb()
1341 unsigned int cpu_port = priv->hw_info->cpu_port; in gswip_port_fdb()
1342 int fid = -1; in gswip_port_fdb()
1347 return -EINVAL; in gswip_port_fdb()
1349 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { in gswip_port_fdb()
1350 if (priv->vlans[i].bridge == bridge) { in gswip_port_fdb()
1351 fid = priv->vlans[i].fid; in gswip_port_fdb()
1356 if (fid == -1) { in gswip_port_fdb()
1357 dev_err(priv->dev, "Port not part of a bridge\n"); in gswip_port_fdb()
1358 return -EINVAL; in gswip_port_fdb()
1373 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); in gswip_port_fdb()
1393 struct gswip_priv *priv = ds->priv; in gswip_port_fdb_dump()
1405 dev_err(priv->dev, "failed to write mac bridge: %d\n", in gswip_port_fdb_dump()
1445 if (!phy_interface_mode_is_rgmii(state->interface) && in gswip_phylink_validate()
1446 state->interface != PHY_INTERFACE_MODE_MII && in gswip_phylink_validate()
1447 state->interface != PHY_INTERFACE_MODE_REVMII && in gswip_phylink_validate()
1448 state->interface != PHY_INTERFACE_MODE_RMII) in gswip_phylink_validate()
1454 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) in gswip_phylink_validate()
1458 if (!phy_interface_mode_is_rgmii(state->interface) && in gswip_phylink_validate()
1459 state->interface != PHY_INTERFACE_MODE_INTERNAL) in gswip_phylink_validate()
1464 dev_err(ds->dev, "Unsupported port: %i\n", port); in gswip_phylink_validate()
1477 if (state->interface != PHY_INTERFACE_MODE_MII && in gswip_phylink_validate()
1478 state->interface != PHY_INTERFACE_MODE_REVMII && in gswip_phylink_validate()
1479 state->interface != PHY_INTERFACE_MODE_RMII) { in gswip_phylink_validate()
1491 bitmap_and(state->advertising, state->advertising, mask, in gswip_phylink_validate()
1497 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", in gswip_phylink_validate()
1498 phy_modes(state->interface), port); in gswip_phylink_validate()
1612 struct gswip_priv *priv = ds->priv; in gswip_phylink_mac_config()
1617 switch (state->interface) { in gswip_phylink_mac_config()
1635 dev_err(ds->dev, in gswip_phylink_mac_config()
1636 "Unsupported interface: %d\n", state->interface); in gswip_phylink_mac_config()
1645 switch (state->interface) { in gswip_phylink_mac_config()
1665 struct gswip_priv *priv = ds->priv; in gswip_phylink_mac_link_down()
1680 struct gswip_priv *priv = ds->priv; in gswip_phylink_mac_link_up()
1720 dev_err(priv->dev, "timeout while reading table: %u, index: %u", in gswip_bcm_ram_entry_read()
1734 struct gswip_priv *priv = ds->priv; in gswip_get_ethtool_stats()
1743 rmon_cnt->offset); in gswip_get_ethtool_stats()
1744 if (rmon_cnt->size == 2) { in gswip_get_ethtool_stats()
1746 rmon_cnt->offset + 1); in gswip_get_ethtool_stats()
1801 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL },
1802 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data },
1803 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data },
1804 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data },
1805 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data },
1811 struct device *dev = priv->dev; in gswip_gphy_fw_load()
1819 ret = clk_prepare_enable(gphy_fw->clk_gate); in gswip_gphy_fw_load()
1823 reset_control_assert(gphy_fw->reset); in gswip_gphy_fw_load()
1825 ret = request_firmware(&fw, gphy_fw->fw_name, dev); in gswip_gphy_fw_load()
1828 gphy_fw->fw_name, ret); in gswip_gphy_fw_load()
1835 size = fw->size + XRX200_GPHY_FW_ALIGN; in gswip_gphy_fw_load()
1841 memcpy(fw_addr, fw->data, fw->size); in gswip_gphy_fw_load()
1845 return -ENOMEM; in gswip_gphy_fw_load()
1850 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); in gswip_gphy_fw_load()
1854 reset_control_deassert(gphy_fw->reset); in gswip_gphy_fw_load()
1863 struct device *dev = priv->dev; in gswip_gphy_fw_probe()
1870 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); in gswip_gphy_fw_probe()
1871 if (IS_ERR(gphy_fw->clk_gate)) { in gswip_gphy_fw_probe()
1873 return PTR_ERR(gphy_fw->clk_gate); in gswip_gphy_fw_probe()
1876 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); in gswip_gphy_fw_probe()
1880 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); in gswip_gphy_fw_probe()
1887 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; in gswip_gphy_fw_probe()
1890 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; in gswip_gphy_fw_probe()
1894 return -EINVAL; in gswip_gphy_fw_probe()
1897 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); in gswip_gphy_fw_probe()
1898 if (IS_ERR(gphy_fw->reset)) { in gswip_gphy_fw_probe()
1899 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) in gswip_gphy_fw_probe()
1901 return PTR_ERR(gphy_fw->reset); in gswip_gphy_fw_probe()
1913 if (!gphy_fw->fw_name) in gswip_gphy_fw_remove()
1916 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); in gswip_gphy_fw_remove()
1918 dev_err(priv->dev, "can not reset GPHY FW pointer"); in gswip_gphy_fw_remove()
1920 clk_disable_unprepare(gphy_fw->clk_gate); in gswip_gphy_fw_remove()
1922 reset_control_put(gphy_fw->reset); in gswip_gphy_fw_remove()
1928 struct device *dev = priv->dev; in gswip_gphy_fw_list()
1938 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { in gswip_gphy_fw_list()
1941 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; in gswip_gphy_fw_list()
1944 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; in gswip_gphy_fw_list()
1948 return -ENOENT; in gswip_gphy_fw_list()
1953 if (match && match->data) in gswip_gphy_fw_list()
1954 priv->gphy_fw_name_cfg = match->data; in gswip_gphy_fw_list()
1956 if (!priv->gphy_fw_name_cfg) { in gswip_gphy_fw_list()
1958 return -ENOENT; in gswip_gphy_fw_list()
1961 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); in gswip_gphy_fw_list()
1962 if (!priv->num_gphy_fw) in gswip_gphy_fw_list()
1963 return -ENOENT; in gswip_gphy_fw_list()
1965 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, in gswip_gphy_fw_list()
1967 if (IS_ERR(priv->rcu_regmap)) in gswip_gphy_fw_list()
1968 return PTR_ERR(priv->rcu_regmap); in gswip_gphy_fw_list()
1970 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, in gswip_gphy_fw_list()
1971 sizeof(*priv->gphy_fw), in gswip_gphy_fw_list()
1973 if (!priv->gphy_fw) in gswip_gphy_fw_list()
1974 return -ENOMEM; in gswip_gphy_fw_list()
1977 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], in gswip_gphy_fw_list()
1988 * taken out of reset. For the SoC-internal GPHY variant there in gswip_gphy_fw_list()
1999 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_gphy_fw_list()
2000 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_gphy_fw_list()
2008 struct device *dev = &pdev->dev; in gswip_probe()
2015 return -ENOMEM; in gswip_probe()
2017 priv->gswip = devm_platform_ioremap_resource(pdev, 0); in gswip_probe()
2018 if (IS_ERR(priv->gswip)) in gswip_probe()
2019 return PTR_ERR(priv->gswip); in gswip_probe()
2021 priv->mdio = devm_platform_ioremap_resource(pdev, 1); in gswip_probe()
2022 if (IS_ERR(priv->mdio)) in gswip_probe()
2023 return PTR_ERR(priv->mdio); in gswip_probe()
2025 priv->mii = devm_platform_ioremap_resource(pdev, 2); in gswip_probe()
2026 if (IS_ERR(priv->mii)) in gswip_probe()
2027 return PTR_ERR(priv->mii); in gswip_probe()
2029 priv->hw_info = of_device_get_match_data(dev); in gswip_probe()
2030 if (!priv->hw_info) in gswip_probe()
2031 return -EINVAL; in gswip_probe()
2033 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in gswip_probe()
2034 if (!priv->ds) in gswip_probe()
2035 return -ENOMEM; in gswip_probe()
2037 priv->ds->dev = dev; in gswip_probe()
2038 priv->ds->num_ports = priv->hw_info->max_ports; in gswip_probe()
2039 priv->ds->priv = priv; in gswip_probe()
2040 priv->ds->ops = &gswip_switch_ops; in gswip_probe()
2041 priv->dev = dev; in gswip_probe()
2045 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); in gswip_probe()
2056 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); in gswip_probe()
2065 err = dsa_register_switch(priv->ds); in gswip_probe()
2070 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { in gswip_probe()
2072 priv->hw_info->cpu_port); in gswip_probe()
2073 err = -EINVAL; in gswip_probe()
2086 dsa_unregister_switch(priv->ds); in gswip_probe()
2089 mdiobus_unregister(priv->ds->slave_mii_bus); in gswip_probe()
2092 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_probe()
2093 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_probe()
2105 dsa_unregister_switch(priv->ds); in gswip_remove()
2107 if (priv->ds->slave_mii_bus) { in gswip_remove()
2108 mdiobus_unregister(priv->ds->slave_mii_bus); in gswip_remove()
2109 of_node_put(priv->ds->slave_mii_bus->dev.of_node); in gswip_remove()
2110 mdiobus_free(priv->ds->slave_mii_bus); in gswip_remove()
2113 for (i = 0; i < priv->num_gphy_fw; i++) in gswip_remove()
2114 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); in gswip_remove()
2125 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 },
2147 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");