Lines Matching +full:rx +full:- +full:internal +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/delay.h>
18 #include <dt-bindings/net/ti-dp83867.h>
185 struct net_device *ndev = phydev->attached_dev; in dp83867_set_wol()
192 if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST | in dp83867_set_wol()
197 if (wol->wolopts & WAKE_MAGIC) { in dp83867_set_wol()
198 mac = (u8 *)ndev->dev_addr; in dp83867_set_wol()
201 return -EINVAL; in dp83867_set_wol()
215 if (wol->wolopts & WAKE_MAGICSECURE) { in dp83867_set_wol()
217 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83867_set_wol()
219 (wol->sopass[3] << 8) | wol->sopass[2]); in dp83867_set_wol()
221 (wol->sopass[5] << 8) | wol->sopass[4]); in dp83867_set_wol()
228 if (wol->wolopts & WAKE_UCAST) in dp83867_set_wol()
233 if (wol->wolopts & WAKE_BCAST) in dp83867_set_wol()
253 wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC | in dp83867_get_wol()
255 wol->wolopts = 0; in dp83867_get_wol()
260 wol->wolopts |= WAKE_UCAST; in dp83867_get_wol()
263 wol->wolopts |= WAKE_BCAST; in dp83867_get_wol()
266 wol->wolopts |= WAKE_MAGIC; in dp83867_get_wol()
271 wol->sopass[0] = (sopass_val & 0xff); in dp83867_get_wol()
272 wol->sopass[1] = (sopass_val >> 8); in dp83867_get_wol()
276 wol->sopass[2] = (sopass_val & 0xff); in dp83867_get_wol()
277 wol->sopass[3] = (sopass_val >> 8); in dp83867_get_wol()
281 wol->sopass[4] = (sopass_val & 0xff); in dp83867_get_wol()
282 wol->sopass[5] = (sopass_val >> 8); in dp83867_get_wol()
284 wol->wolopts |= WAKE_MAGICSECURE; in dp83867_get_wol()
288 wol->wolopts = 0; in dp83867_get_wol()
295 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in dp83867_config_intr()
328 phydev->duplex = DUPLEX_FULL; in dp83867_read_status()
330 phydev->duplex = DUPLEX_HALF; in dp83867_read_status()
333 phydev->speed = SPEED_1000; in dp83867_read_status()
335 phydev->speed = SPEED_100; in dp83867_read_status()
337 phydev->speed = SPEED_10; in dp83867_read_status()
367 return -EINVAL; in dp83867_get_downshift()
380 return -E2BIG; in dp83867_set_downshift()
402 return -EINVAL; in dp83867_set_downshift()
416 switch (tuna->id) { in dp83867_get_tunable()
420 return -EOPNOTSUPP; in dp83867_get_tunable()
427 switch (tuna->id) { in dp83867_set_tunable()
431 return -EOPNOTSUPP; in dp83867_set_tunable()
438 (struct dp83867_private *)phydev->priv; in dp83867_config_port_mirroring()
440 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN) in dp83867_config_port_mirroring()
451 struct dp83867_private *dp83867 = phydev->priv; in dp83867_verify_rgmii_cfg()
453 /* Existing behavior was to use default pin strapping delay in rgmii in dp83867_verify_rgmii_cfg()
454 * mode, but rgmii should have meant no delay. Warn existing users. in dp83867_verify_rgmii_cfg()
456 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { in dp83867_verify_rgmii_cfg()
467 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n" in dp83867_verify_rgmii_cfg()
468 "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n", in dp83867_verify_rgmii_cfg()
472 /* RX delay *must* be specified if internal delay of RX is used. */ in dp83867_verify_rgmii_cfg()
473 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
474 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) && in dp83867_verify_rgmii_cfg()
475 dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
476 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
477 return -EINVAL; in dp83867_verify_rgmii_cfg()
480 /* TX delay *must* be specified if internal delay of TX is used. */ in dp83867_verify_rgmii_cfg()
481 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || in dp83867_verify_rgmii_cfg()
482 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) && in dp83867_verify_rgmii_cfg()
483 dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) { in dp83867_verify_rgmii_cfg()
484 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
485 return -EINVAL; in dp83867_verify_rgmii_cfg()
494 struct dp83867_private *dp83867 = phydev->priv; in dp83867_of_init()
495 struct device *dev = &phydev->mdio.dev; in dp83867_of_init()
496 struct device_node *of_node = dev->of_node; in dp83867_of_init()
500 return -ENODEV; in dp83867_of_init()
503 ret = of_property_read_u32(of_node, "ti,clk-output-sel", in dp83867_of_init()
504 &dp83867->clk_output_sel); in dp83867_of_init()
507 dp83867->set_clk_output = true; in dp83867_of_init()
511 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK && in dp83867_of_init()
512 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) { in dp83867_of_init()
513 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
514 dp83867->clk_output_sel); in dp83867_of_init()
515 return -EINVAL; in dp83867_of_init()
519 if (of_property_read_bool(of_node, "ti,max-output-impedance")) in dp83867_of_init()
520 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX; in dp83867_of_init()
521 else if (of_property_read_bool(of_node, "ti,min-output-impedance")) in dp83867_of_init()
522 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN; in dp83867_of_init()
524 dp83867->io_impedance = -1; /* leave at default */ in dp83867_of_init()
526 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node, in dp83867_of_init()
527 "ti,dp83867-rxctrl-strap-quirk"); in dp83867_of_init()
529 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node, in dp83867_of_init()
530 "ti,sgmii-ref-clock-output-enable"); in dp83867_of_init()
532 dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV; in dp83867_of_init()
533 ret = of_property_read_u32(of_node, "ti,rx-internal-delay", in dp83867_of_init()
534 &dp83867->rx_id_delay); in dp83867_of_init()
535 if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) { in dp83867_of_init()
537 "ti,rx-internal-delay value of %u out of range\n", in dp83867_of_init()
538 dp83867->rx_id_delay); in dp83867_of_init()
539 return -EINVAL; in dp83867_of_init()
542 dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV; in dp83867_of_init()
543 ret = of_property_read_u32(of_node, "ti,tx-internal-delay", in dp83867_of_init()
544 &dp83867->tx_id_delay); in dp83867_of_init()
545 if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) { in dp83867_of_init()
547 "ti,tx-internal-delay value of %u out of range\n", in dp83867_of_init()
548 dp83867->tx_id_delay); in dp83867_of_init()
549 return -EINVAL; in dp83867_of_init()
552 if (of_property_read_bool(of_node, "enet-phy-lane-swap")) in dp83867_of_init()
553 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN; in dp83867_of_init()
555 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap")) in dp83867_of_init()
556 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS; in dp83867_of_init()
558 ret = of_property_read_u32(of_node, "ti,fifo-depth", in dp83867_of_init()
559 &dp83867->tx_fifo_depth); in dp83867_of_init()
561 ret = of_property_read_u32(of_node, "tx-fifo-depth", in dp83867_of_init()
562 &dp83867->tx_fifo_depth); in dp83867_of_init()
564 dp83867->tx_fifo_depth = in dp83867_of_init()
568 if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
569 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
570 dp83867->tx_fifo_depth); in dp83867_of_init()
571 return -EINVAL; in dp83867_of_init()
574 ret = of_property_read_u32(of_node, "rx-fifo-depth", in dp83867_of_init()
575 &dp83867->rx_fifo_depth); in dp83867_of_init()
577 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB; in dp83867_of_init()
579 if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) { in dp83867_of_init()
580 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
581 dp83867->rx_fifo_depth); in dp83867_of_init()
582 return -EINVAL; in dp83867_of_init()
598 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), in dp83867_probe()
601 return -ENOMEM; in dp83867_probe()
603 phydev->priv = dp83867; in dp83867_probe()
610 struct dp83867_private *dp83867 = phydev->priv; in dp83867_config_init()
612 u16 delay; in dp83867_config_init() local
625 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
632 * be set to 0x2. This may causes the PHY link to be unstable - in dp83867_config_init()
644 phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
650 val |= (dp83867->tx_fifo_depth << in dp83867_config_init()
653 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
655 val |= (dp83867->rx_fifo_depth << in dp83867_config_init()
673 * internal testing mode and disable RGMII transmission. in dp83867_config_init()
687 /* If rgmii mode with no internal delay is selected, we do NOT use in dp83867_config_init()
690 * internal delay with a value of 7 (2.00 ns). in dp83867_config_init()
697 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) in dp83867_config_init()
700 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) in dp83867_config_init()
703 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) in dp83867_config_init()
708 delay = 0; in dp83867_config_init()
709 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV) in dp83867_config_init()
710 delay |= dp83867->rx_id_delay; in dp83867_config_init()
711 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV) in dp83867_config_init()
712 delay |= dp83867->tx_id_delay << in dp83867_config_init()
716 delay); in dp83867_config_init()
720 if (dp83867->io_impedance >= 0) in dp83867_config_init()
723 dp83867->io_impedance); in dp83867_config_init()
725 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_config_init()
752 /* SGMII type is set to 4-wire mode by default. in dp83867_config_init()
754 * switch on 6-wire mode. in dp83867_config_init()
756 if (dp83867->sgmii_ref_clk_en) in dp83867_config_init()
766 if (dp83867->rxctrl_strap_quirk) in dp83867_config_init()
779 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP) in dp83867_config_init()
783 if (dp83867->set_clk_output) { in dp83867_config_init()
786 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) { in dp83867_config_init()
790 val = dp83867->clk_output_sel << in dp83867_config_init()
839 * hence no new in-band message from PHY to MAC side SGMII. in dp83867_link_change_notify()
842 * SGMII wouldn`t receive new in-band message from TI PHY with in dp83867_link_change_notify()
844 * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg in dp83867_link_change_notify()
847 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in dp83867_link_change_notify()