Lines Matching +full:clock +full:- +full:generator

1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
103 #define	X1CLK		0x0	/* x1 clock mode */
104 #define	X16CLK		0x40	/* x16 clock mode */
105 #define	X32CLK		0x80	/* x32 clock mode */
106 #define	X64CLK		0xC0	/* x64 clock mode */
112 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
150 /* Write Register 11 (Clock Mode control) */
152 #define	TRxCTC	1	/* TRxC = Transmit clock */
153 #define	TRxCBR	2	/* TRxC = BR Generator Output */
156 #define	TCRTxCP	0	/* Transmit clock = RTxC pin */
157 #define	TCTRxCP	8	/* Transmit clock = TRxC pin */
158 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
159 #define	TCDPLL	0x18	/* Transmit clock = DPLL output */
160 #define	RCRTxCP	0	/* Receive clock = RTxC pin */
161 #define	RCTRxCP	0x20	/* Receive clock = TRxC pin */
162 #define	RCBR	0x40	/* Receive clock = BR Generator output */
163 #define	RCDPLL	0x60	/* Receive clock = DPLL output */
166 /* Write Register 12 (lower byte of baud rate generator time constant) */
168 /* Write Register 13 (upper byte of baud rate generator time constant) */
171 #define	BRENABL	1	/* Baud rate generator enable */
172 #define	BRSRC	2	/* Baud rate generator source */
177 #define	RMC	0x40	/* Reset missing clock */
179 #define	SSBR	0x80	/* Set DPLL source = BR generator */
222 /* Read Register 2 (channel b only) - Interrupt vector */
238 #define	CLK1MIS	0x80		/* One clock missing */
240 /* Read Register 12 (lower byte of baud rate generator constant) */
242 /* Read Register 13 (upper byte of baud rate generator constant) */
320 	u32		rx_overrun;		/* Overruns - not done yet */
353 	/* We need to know the current clock divisor
383 #define Z85C30	1	/* CMOS - better */
386 	int active;	/* Soft interrupt enable - the Mac doesn't 
432  * Events are used to schedule things to happen at timer-interrupt