Lines Matching +full:16 +full:- +full:bits
1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
29 * struct pci_bridge_reg_behavior - register bits behaviors
30 * @ro: Read-Only bits
31 * @rw: Read-Write bits
32 * @w1c: Write-1-to-Clear bits
34 * Reads and Writes will be filtered by specified behavior. All other bits not
37 * multi-bit fields) when read".
40 /* Read-only bits */
43 /* Read-write bits */
46 /* Write-1-to-clear bits */
61 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
62 .w1c = PCI_STATUS_ERROR_BITS << 16,
67 * Cache Line Size register: implement as read-only, we do not
71 * Latency Timer Register: implemented as read-only, as "A
74 * hardwire the Latency Timer to a value of 16 or less"
76 * Header Type: always read-only
78 * BIST register: implemented as read-only, as "A bridge that
80 * read-only register that returns 0 when read"
86 * read-only registers that return 0 when read.
94 /* Secondary latency is read-only */
99 /* The high four bits of I/O base/limit are RW */
102 /* The low four bits of I/O base/limit are RO */
104 PCI_STATUS_DEVSEL_MASK) << 16) |
107 .w1c = PCI_STATUS_ERROR_BITS << 16,
111 /* The high 12-bits of mem base/limit are RW */
114 /* The low four bits of mem base/limit are RO */
115 .ro = GENMASK(19, 16) | GENMASK(3, 0),
119 /* The high 12-bits of pref mem base/limit are RW */
122 /* The low four bits of pref mem base/limit are RO */
123 .ro = GENMASK(19, 16) | GENMASK(3, 0),
144 * be implemented as read-only register that return 0 when read, same
152 * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
153 * are RO, and bridge control (31:16) are a mix of RW, RO,
154 * reserved and W1C bits
165 BIT(8) | BIT(9) | BIT(11)) << 16)),
168 .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
170 .w1c = BIT(10) << 16,
179 * bits [14:0] of Capabilities register are all read-only.
187 * Bits [31:29] and [17:16] are reserved.
188 * Bits [27:18] are reserved for non-upstream ports.
189 * Bits 28 and [14:6] are reserved for non-endpoint devices.
190 * Other bits are read-only.
198 * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
203 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
204 * the rest is reserved. Also bit 6 is reserved for non-upstream
207 .w1c = GENMASK(3, 0) << 16,
208 .ro = GENMASK(5, 4) << 16,
213 * All bits are RO, except bit 23 which is reserved and
214 * bit 18 which is reserved for non-upstream ports.
221 * Link control has bits [15:14], [11:3] and [1:0] RW, the
222 * rest is reserved. Bit 8 is reserved for non-upstream ports.
224 * Link status has bits [13:0] RO, and bits [15:14]
228 .ro = GENMASK(13, 0) << 16,
229 .w1c = GENMASK(15, 14) << 16,
238 * Slot control has bits [14:0] RW, the rest is
241 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
247 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
249 PCI_EXP_SLTSTA_EIS) << 16,
254 * Root control has bits [4:0] RW, the rest is
262 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
267 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
279 * (typically at least vendor, device, revision), the ->ops pointer,
280 * and optionally ->data and ->has_pcie.
285 BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END); in pci_bridge_emul_init()
287 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16); in pci_bridge_emul_init()
288 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE; in pci_bridge_emul_init()
289 bridge->conf.cache_line_size = 0x10; in pci_bridge_emul_init()
290 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST); in pci_bridge_emul_init()
291 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior, in pci_bridge_emul_init()
294 if (!bridge->pci_regs_behavior) in pci_bridge_emul_init()
295 return -ENOMEM; in pci_bridge_emul_init()
297 if (bridge->has_pcie) { in pci_bridge_emul_init()
298 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START; in pci_bridge_emul_init()
299 bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST); in pci_bridge_emul_init()
300 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP; in pci_bridge_emul_init()
301 bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4); in pci_bridge_emul_init()
302 bridge->pcie_cap_regs_behavior = in pci_bridge_emul_init()
306 if (!bridge->pcie_cap_regs_behavior) { in pci_bridge_emul_init()
307 kfree(bridge->pci_regs_behavior); in pci_bridge_emul_init()
308 return -ENOMEM; in pci_bridge_emul_init()
310 /* These bits are applicable only for PCI and reserved on PCIe */ in pci_bridge_emul_init()
311 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &= in pci_bridge_emul_init()
313 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &= in pci_bridge_emul_init()
318 PCI_STATUS_DEVSEL_MASK) << 16); in pci_bridge_emul_init()
319 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &= in pci_bridge_emul_init()
321 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &= in pci_bridge_emul_init()
323 PCI_STATUS_DEVSEL_MASK) << 16); in pci_bridge_emul_init()
324 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &= in pci_bridge_emul_init()
326 BIT(8) | BIT(9) | BIT(11)) << 16); in pci_bridge_emul_init()
327 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &= in pci_bridge_emul_init()
328 ~((PCI_BRIDGE_CTL_FAST_BACK) << 16); in pci_bridge_emul_init()
329 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &= in pci_bridge_emul_init()
330 ~(BIT(10) << 16); in pci_bridge_emul_init()
334 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0; in pci_bridge_emul_init()
335 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0; in pci_bridge_emul_init()
348 if (bridge->has_pcie) in pci_bridge_emul_cleanup()
349 kfree(bridge->pcie_cap_regs_behavior); in pci_bridge_emul_cleanup()
350 kfree(bridge->pci_regs_behavior); in pci_bridge_emul_cleanup()
357 * ->ops->read_base or ->ops->read_pcie operations.
369 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) { in pci_bridge_emul_conf_read()
374 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) { in pci_bridge_emul_conf_read()
379 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { in pci_bridge_emul_conf_read()
380 reg -= PCI_CAP_PCIE_START; in pci_bridge_emul_conf_read()
381 read_op = bridge->ops->read_pcie; in pci_bridge_emul_conf_read()
382 cfgspace = (__le32 *) &bridge->pcie_conf; in pci_bridge_emul_conf_read()
383 behavior = bridge->pcie_cap_regs_behavior; in pci_bridge_emul_conf_read()
385 read_op = bridge->ops->read_base; in pci_bridge_emul_conf_read()
386 cfgspace = (__le32 *) &bridge->conf; in pci_bridge_emul_conf_read()
387 behavior = bridge->pci_regs_behavior; in pci_bridge_emul_conf_read()
419 * ->ops->write_base or ->ops->write_pcie operations.
431 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) in pci_bridge_emul_conf_write()
434 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) in pci_bridge_emul_conf_write()
452 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) { in pci_bridge_emul_conf_write()
453 reg -= PCI_CAP_PCIE_START; in pci_bridge_emul_conf_write()
454 write_op = bridge->ops->write_pcie; in pci_bridge_emul_conf_write()
455 cfgspace = (__le32 *) &bridge->pcie_conf; in pci_bridge_emul_conf_write()
456 behavior = bridge->pcie_cap_regs_behavior; in pci_bridge_emul_conf_write()
458 write_op = bridge->ops->write_base; in pci_bridge_emul_conf_write()
459 cfgspace = (__le32 *) &bridge->conf; in pci_bridge_emul_conf_write()
460 behavior = bridge->pci_regs_behavior; in pci_bridge_emul_conf_write()
463 /* Keep all bits, except the RW bits */ in pci_bridge_emul_conf_write()
466 /* Update the value of the RW bits */ in pci_bridge_emul_conf_write()
469 /* Clear the W1C bits */ in pci_bridge_emul_conf_write()
472 /* Save the new value with the cleared W1C bits into the cfgspace */ in pci_bridge_emul_conf_write()
476 * Clear the W1C bits not specified by the write mask, so that the in pci_bridge_emul_conf_write()
482 * Set the W1C bits specified by the write mask, so that write_op() in pci_bridge_emul_conf_write()