Lines Matching +full:pci +full:- +full:host +full:- +full:cam +full:- +full:generic
1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
4 * Devices present only on certain architectures (host bridges et cetera)
5 * should be handled in arch-specific code.
11 * Init/reset quirks for USB host controllers should be in the USB quirks
18 #include <linux/pci.h>
34 #include "pci.h"
64 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
65 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
66 (f->vendor == dev->vendor || in pci_do_fixups()
67 f->vendor == (u16) PCI_ANY_ID) && in pci_do_fixups()
68 (f->device == dev->device || in pci_do_fixups()
69 f->device == (u16) PCI_ANY_ID)) { in pci_do_fixups()
72 hook = offset_to_ptr(&f->hook_offset); in pci_do_fixups()
74 hook = f->hook; in pci_do_fixups()
163 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); in pci_apply_final_quirks()
170 * value shared by all PCI devices. If there's a in pci_apply_final_quirks()
188 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, in pci_apply_final_quirks()
198 * Decoding should be disabled for a PCI device during BAR sizing to avoid
199 * conflict. But doing so may cause problems on host bridge and perhaps other
200 * key system devices. For devices that need to have mmio decoding always-on,
201 * we need to set the dev->mmio_always_on bit.
205 dev->mmio_always_on = 1; in quirk_mmio_always_on()
217 bus = pdev->bus; in aspeed_fixup_vgaarb()
218 bridge = bus->self; in aspeed_fixup_vgaarb()
224 /* Yes, this bridge is PCI bridge-to-bridge spec compliant, in aspeed_fixup_vgaarb()
230 dev_warn(&pdev->dev, "VGA bridge control is not enabled\n"); in aspeed_fixup_vgaarb()
239 if (vdevp->vendor != 0x1a03) { in aspeed_fixup_vgaarb()
241 dev_info(&pdev->dev, "Another boot vga device: 0x%x:0x%x\n", in aspeed_fixup_vgaarb()
242 vdevp->vendor, vdevp->device); in aspeed_fixup_vgaarb()
249 dev_info(&pdev->dev, "Boot vga device set as 0x%x:0x%x\n", in aspeed_fixup_vgaarb()
250 pdev->vendor, pdev->device); in aspeed_fixup_vgaarb()
256 * device with a broken_parity_status to allow PCI scanning code to "skip"
261 dev->broken_parity_status = 1; /* This device gives false positives */ in quirk_mellanox_tavor()
294 * contacts at VIA ask them for me please -- Alan
338 /* Chipsets where PCI->PCI transfers vanish or hang */
342 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); in quirk_nopcipci()
355 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); in quirk_nopciamd()
365 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_triton()
375 * VIA Apollo KT133 needs PCI latency patch
376 * Made according to a Windows driver-based patch by George E. Breese;
377 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
378 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on
397 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; in quirk_vialatency()
401 if (p->revision < 0x40 || p->revision > 0x42) in quirk_vialatency()
409 if (p->revision < 0x10 || p->revision > 0x12) in quirk_vialatency()
414 * Ok we have the problem. Now set the PCI master grant to occur in quirk_vialatency()
415 * every master grant. The apparent bug is that under high PCI load in quirk_vialatency()
429 * "Master priority rotation on every PCI master grant" in quirk_vialatency()
450 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_viaetbf()
459 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_vsfx()
473 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_alimagik()
484 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); in quirk_natoma()
496 * This chip can cause PCI parity errors if config register 0xA0 is read
501 dev->cfg_size = 0xA0; in quirk_citrine()
511 dev->cfg_size = 0x600; in quirk_nfp6000()
524 struct resource *r = &dev->resource[i]; in quirk_extend_bar_to_page()
526 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { in quirk_extend_bar_to_page()
527 r->end = PAGE_SIZE - 1; in quirk_extend_bar_to_page()
528 r->start = 0; in quirk_extend_bar_to_page()
529 r->flags |= IORESOURCE_UNSET; in quirk_extend_bar_to_page()
539 * If it's needed, re-allocate the region.
543 struct resource *r = &dev->resource[0]; in quirk_s3_64M()
545 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) { in quirk_s3_64M()
546 r->flags |= IORESOURCE_UNSET; in quirk_s3_64M()
547 r->start = 0; in quirk_s3_64M()
548 r->end = 0x3ffffff; in quirk_s3_64M()
559 struct resource *res = dev->resource + pos; in quirk_io()
566 res->name = pci_name(dev); in quirk_io()
567 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; in quirk_io()
568 res->flags |= in quirk_io()
570 region &= ~(size - 1); in quirk_io()
572 /* Convert from PCI bus to resource space */ in quirk_io()
574 bus_region.end = region + size - 1; in quirk_io()
575 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io()
583 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
587 * CS553x's ISA PCI BARs may also be read-only (ref:
588 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
609 struct resource *res = dev->resource + nr; in quirk_io_region()
612 region &= ~(size - 1); in quirk_io_region()
617 res->name = pci_name(dev); in quirk_io_region()
618 res->flags = IORESOURCE_IO; in quirk_io_region()
620 /* Convert from PCI bus to resource space */ in quirk_io_region()
622 bus_region.end = region + size - 1; in quirk_io_region()
623 pcibios_bus_to_resource(dev->bus, res, &bus_region); in quirk_io_region()
631 * between 0x3b0->0x3bb or read 0x3d3
649 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
650 * defines as "USB device (not host controller)". The dwc3 driver can then
655 u32 class = pdev->class; in quirk_amd_dwc_class()
658 /* Use "USB Device (not host controller)" class */ in quirk_amd_dwc_class()
659 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_amd_dwc_class()
661 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", in quirk_amd_dwc_class()
662 class, pdev->class); in quirk_amd_dwc_class()
671 * Synopsys USB 3.x host HAPS platform has a class code of
673 * devices should use dwc3-haps driver. Change these devices' class code to
674 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
679 u32 class = pdev->class; in quirk_synopsys_haps()
681 switch (pdev->device) { in quirk_synopsys_haps()
685 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; in quirk_synopsys_haps()
686 …pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhc… in quirk_synopsys_haps()
687 class, pdev->class); in quirk_synopsys_haps()
734 base &= -size; in piix4_io_quirk()
735 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); in piix4_io_quirk()
760 base &= -size; in piix4_mem_quirk()
761 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); in piix4_mem_quirk()
813 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
887 base &= ~(size-1); in ich6_lpc_generic_decode()
893 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); in ich6_lpc_generic_decode()
901 /* ICH6-specific generic IO decode */ in quirk_ich6_lpc()
902 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); in quirk_ich6_lpc()
903 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); in quirk_ich6_lpc()
920 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ in ich7_lpc_generic_decode()
932 /* ICH7-10 has the same common LPC generic IO decode registers */
938 /* And have 4 ICH7+ generic decodes */ in quirk_ich7_lpc()
939 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); in quirk_ich7_lpc()
940 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); in quirk_ich7_lpc()
941 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); in quirk_ich7_lpc()
942 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); in quirk_ich7_lpc()
964 if (dev->revision & 0x10) in quirk_vt82c586_acpi()
981 "vt82c686 HW-mon"); in quirk_vt82c686_acpi()
1000 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast
1001 * back-to-back: Disable fast back-to-back on the secondary bus segment
1008 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); in quirk_xio2000a()
1009 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { in quirk_xio2000a()
1023 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
1026 * TODO: When we have device-specific interrupt routers, this code will go
1036 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ in quirk_via_ioapic()
1048 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
1060 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); in quirk_via_vt8237_bypass_apic_deassert()
1068 * The AMD IO-APIC can hang the box when an APIC IRQ is masked.
1078 if (dev->revision >= 0x02) { in quirk_amd_ioapic()
1090 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ in quirk_cavium_sriov_rnm_link()
1091 if (dev->subsystem_device == 0xa118) in quirk_cavium_sriov_rnm_link()
1092 dev->sriov->link = dev->devfn; in quirk_cavium_sriov_rnm_link()
1099 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
1103 if (dev->subordinate && dev->revision <= 0x12) { in quirk_amd_8131_mmrbc()
1104 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", in quirk_amd_8131_mmrbc()
1105 dev->revision); in quirk_amd_8131_mmrbc()
1106 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; in quirk_amd_8131_mmrbc()
1116 * -jgarzik
1122 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ in quirk_via_acpi()
1126 d->irq = irq; in quirk_via_acpi()
1132 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
1137 switch (dev->device) { in quirk_via_bridge()
1140 * The VT82C686 is special; it attaches to PCI and can have in quirk_via_bridge()
1144 via_vlink_dev_lo = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1145 via_vlink_dev_hi = PCI_SLOT(dev->devfn); in quirk_via_bridge()
1172 * quirk_via_vlink - VIA VLink IRQ number update
1173 * @dev: PCI device
1176 * the IRQ line register which usually is not relevant for PCI cards, is
1187 if (via_vlink_dev_lo == -1) in quirk_via_vlink()
1190 new_irq = dev->irq; in quirk_via_vlink()
1197 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || in quirk_via_vlink()
1198 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) in quirk_via_vlink()
1223 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); in quirk_vt82c598_id()
1243 * Following the PCI ordering rules is optional on the AMD762. I'm not sure
1255 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); in quirk_amd_ordering()
1266 * DreamWorks-provided workaround for Dunord I-3000 problem
1274 struct resource *r = &dev->resource[1]; in quirk_dunord()
1276 r->flags |= IORESOURCE_UNSET; in quirk_dunord()
1277 r->start = 0; in quirk_dunord()
1278 r->end = 0xffffff; in quirk_dunord()
1283 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive
1285 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01.
1289 dev->transparent = 1; in quirk_transparent_bridge()
1295 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce
1296 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets
1324 if (pdev->revision != 0x04) /* Only C0 requires this */ in quirk_disable_pxb()
1330 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); in quirk_disable_pxb()
1338 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ in quirk_amd_ide_mode()
1349 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; in quirk_amd_ide_mode()
1369 pdev->class &= ~5; in quirk_svwks_csb5ide()
1371 /* PCI layer will sort out resources */ in quirk_svwks_csb5ide()
1376 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */
1386 pdev->class &= ~5; in quirk_ide_samemode()
1395 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; in quirk_no_ata_d3()
1411 * This was originally an Alpha-specific thing, but it really fits here.
1412 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1416 dev->class = PCI_CLASS_BRIDGE_EISA << 8; in quirk_eisa_bridge()
1421 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1423 * users to be irritated by just another PCI Device in the Win98 device
1427 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1429 * becomes necessary to do this tweak in two steps -- the chosen trigger
1430 * is either the Host bridge (preferred) or on-board VGA controller.
1443 * the DSDT and double-check that there is no code accessing the SMBus.
1449 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_smbus_hostbridge()
1450 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) in asus_hides_smbus_hostbridge()
1451 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1452 case 0x8025: /* P4B-LX */ in asus_hides_smbus_hostbridge()
1458 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) in asus_hides_smbus_hostbridge()
1459 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1460 case 0x80b1: /* P4GE-V */ in asus_hides_smbus_hostbridge()
1462 case 0x8093: /* P4B533-V */ in asus_hides_smbus_hostbridge()
1465 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) in asus_hides_smbus_hostbridge()
1466 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1470 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) in asus_hides_smbus_hostbridge()
1471 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1475 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) in asus_hides_smbus_hostbridge()
1476 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1477 case 0x80c9: /* PU-DLS */ in asus_hides_smbus_hostbridge()
1480 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) in asus_hides_smbus_hostbridge()
1481 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1487 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1488 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1493 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1494 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1495 case 0x80f2: /* P4P800-X */ in asus_hides_smbus_hostbridge()
1498 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) in asus_hides_smbus_hostbridge()
1499 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1504 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { in asus_hides_smbus_hostbridge()
1505 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1506 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1511 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) in asus_hides_smbus_hostbridge()
1512 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1518 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) in asus_hides_smbus_hostbridge()
1519 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1523 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { in asus_hides_smbus_hostbridge()
1524 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1525 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1529 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { in asus_hides_smbus_hostbridge()
1530 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) in asus_hides_smbus_hostbridge()
1531 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) in asus_hides_smbus_hostbridge()
1536 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1537 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ in asus_hides_smbus_hostbridge()
1538 /* Motherboard doesn't have Host bridge in asus_hides_smbus_hostbridge()
1540 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1543 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) in asus_hides_smbus_hostbridge()
1544 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1548 /* Motherboard doesn't have Host bridge in asus_hides_smbus_hostbridge()
1549 * subvendor/subdevice IDs and on-board VGA in asus_hides_smbus_hostbridge()
1555 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) in asus_hides_smbus_hostbridge()
1556 switch (dev->subsystem_device) { in asus_hides_smbus_hostbridge()
1558 /* Motherboard doesn't have host bridge in asus_hides_smbus_hostbridge()
1560 * its on-board VGA controller */ in asus_hides_smbus_hostbridge()
1712 dev->device = devid; in quirk_sis_503()
1720 * and MC97 modem controller are disabled when a second PCI soundcard is
1722 * -- bjd
1729 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { in asus_hides_ac97_lpc()
1730 if (dev->device == PCI_DEVICE_ID_VIA_8237) in asus_hides_ac97_lpc()
1755 * early on to make the additional device appear during the PCI scanning.
1763 if (PCI_FUNC(pdev->devfn)) in quirk_jmicron_ata()
1769 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ in quirk_jmicron_ata()
1772 switch (pdev->device) { in quirk_jmicron_ata()
1804 pdev->hdr_type = hdr & 0x7f; in quirk_jmicron_ata()
1805 pdev->multifunction = !!(hdr & 0x80); in quirk_jmicron_ata()
1808 pdev->class = class >> 8; in quirk_jmicron_ata()
1833 if (dev->multifunction) { in quirk_jmicron_async_suspend()
1834 device_disable_async_suspend(&dev->dev); in quirk_jmicron_async_suspend()
1835 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); in quirk_jmicron_async_suspend()
1848 if ((pdev->class >> 8) != 0xff00) in quirk_alder_ioapic()
1852 * The first BAR is the location of the IO-APIC... we must in quirk_alder_ioapic()
1857 insert_resource(&iomem_resource, &pdev->resource[0]); in quirk_alder_ioapic()
1864 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); in quirk_alder_ioapic()
1872 dev->no_msi = 1; in quirk_no_msi()
1883 pdev->no_msi = 1; in quirk_pcie_mch()
1893 * together on certain PXH-based systems.
1897 dev->no_msi = 1; in quirk_pcie_pxh()
1907 * Some Intel PCI Express chipsets have trouble with downstream device
1913 dev->no_d1d2 = 1; in quirk_intel_pcie_pm()
1939 if (dev->d3hot_delay >= delay) in quirk_d3hot_delay()
1942 dev->d3hot_delay = delay; in quirk_d3hot_delay()
1943 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", in quirk_d3hot_delay()
1944 dev->d3hot_delay); in quirk_d3hot_delay()
1949 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && in quirk_radeon_pm()
1950 dev->subsystem_device == 0x00e2) in quirk_radeon_pm()
1960 * to be ineffective on the platforms in question; the PCI device appears to
1961 * remain on in D3hot state. The D3hot-to-D0 transition then requires an
1976 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); in dmi_disable_ioapicreroute()
1987 .ident = "ASUSTek Computer INC. M2N-LR",
1990 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1999 * that a PCI device's interrupt handler is installed on the boot interrupt
2008 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; in quirk_reroute_to_boot_interrupts_intel()
2010 dev->vendor, dev->device); in quirk_reroute_to_boot_interrupts_intel()
2035 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no
2036 * 300641-004US, section 5.7.3.
2038 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003.
2039 * Core IO on Xeon E5 v2, see Intel order no 329188-003.
2040 * Core IO on Xeon E7 v2, see Intel order no 329595-002.
2041 * Core IO on Xeon E5 v3, see Intel order no 330784-003.
2042 * Core IO on Xeon E7 v3, see Intel order no 332315-001US.
2043 * Core IO on Xeon E5 v4, see Intel order no 333810-002US.
2044 * Core IO on Xeon E7 v4, see Intel order no 332315-001US.
2045 * Core IO on Xeon D-1500, see Intel order no 332051-001.
2062 switch (dev->device) { in quirk_disable_intel_boot_interrupt()
2073 case 0x6f28: /* Xeon D-1500 */ in quirk_disable_intel_boot_interrupt()
2085 dev->vendor, dev->device); in quirk_disable_intel_boot_interrupt()
2088 * Device 29 Func 5 Device IDs of IO-APIC
2124 /* Disable boot interrupts on HT-1000 */
2150 dev->vendor, dev->device); in quirk_disable_broadcom_boot_interrupt()
2159 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
2173 if ((dev->revision == AMD_813X_REV_B1) || in quirk_disable_amd_813x_boot_interrupt()
2174 (dev->revision == AMD_813X_REV_B2)) in quirk_disable_amd_813x_boot_interrupt()
2182 dev->vendor, dev->device); in quirk_disable_amd_813x_boot_interrupt()
2201 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2206 dev->vendor, dev->device); in quirk_disable_amd_8111_boot_interrupt()
2213 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
2215 * Re-allocate the region if needed...
2219 struct resource *r = &dev->resource[0]; in quirk_tc86c001_ide()
2221 if (r->start & 0x8) { in quirk_tc86c001_ide()
2222 r->flags |= IORESOURCE_UNSET; in quirk_tc86c001_ide()
2223 r->start = 0; in quirk_tc86c001_ide()
2224 r->end = 0xf; in quirk_tc86c001_ide()
2232 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the
2236 * Re-allocate the regions to a 256-byte boundary if necessary.
2242 /* Fixed in revision 2 (PCI 9052). */ in quirk_plx_pci9050()
2243 if (dev->revision >= 2) in quirk_plx_pci9050()
2248 struct resource *r = &dev->resource[bar]; in quirk_plx_pci9050()
2249 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", in quirk_plx_pci9050()
2251 r->flags |= IORESOURCE_UNSET; in quirk_plx_pci9050()
2252 r->start = 0; in quirk_plx_pci9050()
2253 r->end = 0xff; in quirk_plx_pci9050()
2260 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
2272 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; in quirk_netmos()
2273 unsigned int num_serial = dev->subsystem_device & 0xf; in quirk_netmos()
2285 switch (dev->device) { in quirk_netmos()
2288 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && in quirk_netmos()
2289 dev->subsystem_device == 0x0299) in quirk_netmos()
2298 dev->device, num_parallel, num_serial); in quirk_netmos()
2299 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | in quirk_netmos()
2300 (dev->class & 0xff); in quirk_netmos()
2313 switch (dev->device) { in quirk_e100_interrupt()
2314 /* PCI IDs taken from drivers/net/e100.c */ in quirk_e100_interrupt()
2338 * re-enable them when it's ready. in quirk_e100_interrupt()
2349 if (dev->pm_cap) { in quirk_e100_interrupt()
2350 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in quirk_e100_interrupt()
2355 /* Convert from PCI bus to resource space. */ in quirk_e100_interrupt()
2404 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the
2411 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
2420 dev->clear_retrain_link = 1; in quirk_enable_clear_retrain_link()
2429 u32 class = dev->class; in fixup_rev1_53c810()
2438 dev->class = PCI_CLASS_STORAGE_SCSI << 8; in fixup_rev1_53c810()
2439 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", in fixup_rev1_53c810()
2440 class, dev->class); in fixup_rev1_53c810()
2453 dev->io_window_1k = 1; in quirk_p64h2_1k_io()
2482 * Disable PCI Bus Parking and PCI Master read caching on CX700 in quirk_via_cx700_pci_parking_caching()
2483 * which causes unspecified timing errors with a VT6212L on the PCI in quirk_via_cx700_pci_parking_caching()
2486 * This quirk is only enabled if a second (on the external PCI bus) in quirk_via_cx700_pci_parking_caching()
2487 * VT6212L is found -- the CX700 core itself also contains a USB in quirk_via_cx700_pci_parking_caching()
2488 * host controller with the same PCI ID as the VT6212L. in quirk_via_cx700_pci_parking_caching()
2497 * p should contain the first (internal) VT6212L -- see if we have in quirk_via_cx700_pci_parking_caching()
2507 /* Turn off PCI Bus Parking */ in quirk_via_cx700_pci_parking_caching()
2510 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); in quirk_via_cx700_pci_parking_caching()
2516 /* Turn off PCI Master read caching */ in quirk_via_cx700_pci_parking_caching()
2519 /* Set PCI Master Bus time-out to "1x16 PCLK" */ in quirk_via_cx700_pci_parking_caching()
2525 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); in quirk_via_cx700_pci_parking_caching()
2551 * DRBs - this is where we expose device 6.
2552 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2593 if (dev->subordinate) { in quirk_disable_msi()
2595 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_disable_msi()
2605 * we use the possible vendor/device IDs of the host bridge for the
2612 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); in quirk_amd_780_apc_msi()
2614 if (apc_bridge->device == 0x9602) in quirk_amd_780_apc_msi()
2631 while (pos && ttl--) { in msi_ht_cap_enabled()
2651 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { in quirk_msi_ht_cap()
2653 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_msi_ht_cap()
2667 if (!dev->subordinate) in quirk_nvidia_ck804_msi_ht_cap()
2674 pdev = pci_get_slot(dev->bus, 0); in quirk_nvidia_ck804_msi_ht_cap()
2679 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; in quirk_nvidia_ck804_msi_ht_cap()
2692 while (pos && ttl--) { in ht_enable_msi_mapping()
2713 * The P5N32-SLI motherboards from Asus have a problem with MSI
2722 (strstr(board_name, "P5N32-SLI PREMIUM") || in nvenet_msi_disable()
2723 strstr(board_name, "P5N32-E SLI"))) { in nvenet_msi_disable()
2724 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); in nvenet_msi_disable()
2725 dev->no_msi = 1; in nvenet_msi_disable()
2733 * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
2738 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
2743 dev->no_msi = 1; in pci_quirk_nvidia_tegra_disable_rp_msi()
2824 while (pos && ttl--) { in ht_check_msi_mapping()
2852 dev_no = host_bridge->devfn >> 3; in host_bridge_with_leaf()
2854 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); in host_bridge_with_leaf()
2858 /* found next host bridge? */ in host_bridge_with_leaf()
2910 dev_no = dev->devfn >> 3; in nv_ht_enable_msi_mapping()
2911 for (i = dev_no; i >= 0; i--) { in nv_ht_enable_msi_mapping()
2912 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); in nv_ht_enable_msi_mapping()
2947 while (pos && ttl--) { in ht_disable_msi_mapping()
2980 * a non-Hypertransport host bridge. Locate the host bridge... in __nv_msi_ht_cap_quirk()
2982 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, in __nv_msi_ht_cap_quirk()
2985 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); in __nv_msi_ht_cap_quirk()
2991 /* Host bridge is to HT */ in __nv_msi_ht_cap_quirk()
3006 /* Host bridge is not to HT, disable HT MSI mapping on this device */ in __nv_msi_ht_cap_quirk()
3029 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_bug()
3038 * we need check PCI REVISION ID of SMBus controller to get SB700 in quirk_msi_intx_disable_ati_bug()
3046 if ((p->revision < 0x3B) && (p->revision >= 0x30)) in quirk_msi_intx_disable_ati_bug()
3047 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_ati_bug()
3054 if (dev->revision < 0x18) { in quirk_msi_intx_disable_qca_bug()
3056 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; in quirk_msi_intx_disable_qca_bug()
3120 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
3124 * tested), since currently there is no standard way to disable only MSI-X.
3131 dev->no_msi = 1; in quirk_al_msi_disable()
3132 pci_warn(dev, "Disabling MSI/MSI-X\n"); in quirk_al_msi_disable()
3139 * Allow manual resource allocation for PCI hotplug bridges via
3140 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI
3142 * allocate resources when hotplug device is inserted and PCI bus is
3147 dev->is_hotplug_bridge = 1; in quirk_hotplug_bridge()
3162 * controllers (and PCI functions). The Linux SDHCI driver supports MMC
3164 * MMC controller - so the SDHCI driver never sees them.
3168 * case that the relevant PCI registers to deactivate the MMC controller
3169 * live on PCI function 0, which might be the CardBus controller or the
3173 * other PCI functions shift up one level, e.g. function #2 becomes function
3174 * #1, and this will confuse the PCI core.
3188 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_rl5c476()
3219 if (PCI_FUNC(dev->devfn)) in ricoh_mmc_fixup_r5c832()
3226 * 0x150 - SD2.0 mode enable for changing base clock in ricoh_mmc_fixup_r5c832()
3228 * 0xe1 - Base clock frequency in ricoh_mmc_fixup_r5c832()
3229 * 0x32 - 50Mhz new clock frequency in ricoh_mmc_fixup_r5c832()
3230 * 0xf9 - Key register for 0x150 in ricoh_mmc_fixup_r5c832()
3231 * 0xfc - key register for 0xe1 in ricoh_mmc_fixup_r5c832()
3233 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || in ricoh_mmc_fixup_r5c832()
3234 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { in ricoh_mmc_fixup_r5c832()
3271 * This is a quirk for masking VT-d spec-defined errors to platform error
3274 * on the RAS config settings of the platform) when a VT-d fault happens.
3277 * VT-d spec-related errors are already handled by the VT-d OS code, so no
3293 u32 class = dev->class; in fixup_ti816x_class()
3296 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; in fixup_ti816x_class()
3297 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", in fixup_ti816x_class()
3298 class, dev->class); in fixup_ti816x_class()
3309 dev->pcie_mpss = 1; /* 256 bytes */ in fixup_mpss_256()
3324 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
3360 /* Intel 5000 series memory controllers and ports 2-7 */
3375 /* Intel 5100 series memory controllers and ports 2-7 */
3402 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3408 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1; in quirk_intel_ntb()
3417 * and the interrupt ends up -somewhere-.
3430 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); in disable_igfx_irq()
3452 * PCI devices which are on Intel chips can skip the 10ms delay
3457 dev->d3hot_delay = 0; in quirk_remove_d3hot_delay()
3463 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */
3493 dev->broken_intx_masking = 1; in quirk_broken_intx_masking()
3497 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3503 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3504 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3506 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3513 * DisINTx can be set but the interrupt status bit is non-functional.
3553 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3569 if (pdev->device == mellanox_broken_intx_devs[i]) { in mellanox_check_broken_intx_masking()
3570 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3576 * Getting here means Connect-IB cards and up. Connect-IB has no INTx in mellanox_check_broken_intx_masking()
3579 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) in mellanox_check_broken_intx_masking()
3582 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && in mellanox_check_broken_intx_masking()
3583 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) in mellanox_check_broken_intx_masking()
3586 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ in mellanox_check_broken_intx_masking()
3594 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); in mellanox_check_broken_intx_masking()
3606 …pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW… in mellanox_check_broken_intx_masking()
3607 fw_major, fw_minor, fw_subminor, pdev->device == in mellanox_check_broken_intx_masking()
3609 pdev->broken_intx_masking = 1; in mellanox_check_broken_intx_masking()
3622 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; in quirk_no_bus_reset()
3631 if ((dev->device & 0xffc0) == 0x2340) in quirk_nvidia_no_bus_reset()
3639 * The device will throw a Link Down error on AER-capable systems and
3674 if (!pci_is_root_bus(dev->bus)) in quirk_no_pm_reset()
3675 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; in quirk_no_pm_reset()
3679 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3680 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3690 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset
3691 * (i.e., they advertise NoSoftRst-). However, this transition does not have
3709 if (pdev->is_hotplug_bridge && in quirk_thunderbolt_hotplug_msi()
3710 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || in quirk_thunderbolt_hotplug_msi()
3711 pdev->revision <= 1)) in quirk_thunderbolt_hotplug_msi()
3712 pdev->no_msi = 1; in quirk_thunderbolt_hotplug_msi()
3730 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3734 * bridges leading to the NHI and to the tunnel PCI bridges.
3759 bridge = ACPI_HANDLE(&dev->dev); in quirk_apple_poweroff_thunderbolt()
3766 * device ID as those on the host, but they will not have the in quirk_apple_poweroff_thunderbolt()
3790 * Following are device-specific reset methods which can be used to
3791 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3797 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf in reset_intel_82599_sfp_virtfn()
3827 return -ENOMEM; in reset_ivb_igd()
3858 /* Device-specific reset method for Chelsio T4-based adapters */
3865 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating in reset_chelsio_generic_dev()
3866 * that we have no device-specific reset method. in reset_chelsio_generic_dev()
3868 if ((dev->device & 0xf000) != 0x4000) in reset_chelsio_generic_dev()
3869 return -ENOTTY; in reset_chelsio_generic_dev()
3895 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts in reset_chelsio_generic_dev()
3896 * are disabled when an MSI-X interrupt message needs to be delivered. in reset_chelsio_generic_dev()
3897 * So we briefly re-enable MSI-X interrupts for the duration of the in reset_chelsio_generic_dev()
3899 * MSI-X state. in reset_chelsio_generic_dev()
3901 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); in reset_chelsio_generic_dev()
3903 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, in reset_chelsio_generic_dev()
3912 * the original PCI Configuration Space Command word, and return in reset_chelsio_generic_dev()
3926 * FLR where config space reads from the device return -1. We seem to be
3928 * FLR. This quirk is generic for any NVMe class device requiring similar
3933 * Chapter 2: Required and optional PCI config registers
3943 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || in nvme_disable_and_flr()
3945 return -ENOTTY; in nvme_disable_and_flr()
3952 return -ENOTTY; in nvme_disable_and_flr()
4014 return -ENOTTY; in delay_250ms_after_flr()
4033 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */
4045 return -ENOTTY; in reset_hinic_vf_dev()
4051 return -ENOTTY; in reset_hinic_vf_dev()
4106 * These device-specific reset methods are here rather than in a driver
4107 * because when a host assigns a device to a guest VM, the host may need
4114 for (i = pci_dev_reset_methods; i->reset; i++) { in pci_dev_specific_reset()
4115 if ((i->vendor == dev->vendor || in pci_dev_specific_reset()
4116 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_reset()
4117 (i->device == dev->device || in pci_dev_specific_reset()
4118 i->device == (u16)PCI_ANY_ID)) in pci_dev_specific_reset()
4119 return i->reset(dev, probe); in pci_dev_specific_reset()
4122 return -ENOTTY; in pci_dev_specific_reset()
4127 if (PCI_FUNC(dev->devfn) != 0) in quirk_dma_func0_alias()
4128 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); in quirk_dma_func0_alias()
4141 if (PCI_FUNC(dev->devfn) != 1) in quirk_dma_func1_alias()
4142 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); in quirk_dma_func1_alias()
4200 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
4210 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
4214 * controller supports private devices, which can be hidden from PCI config
4235 pci_add_dma_alias(dev, id->driver_data, 1); in quirk_fixed_dma_alias()
4240 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
4245 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
4246 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
4250 if (!pci_is_root_bus(pdev->bus) && in quirk_use_pcie_bridge_dma_alias()
4251 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && in quirk_use_pcie_bridge_dma_alias()
4252 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && in quirk_use_pcie_bridge_dma_alias()
4253 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) in quirk_use_pcie_bridge_dma_alias()
4254 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; in quirk_use_pcie_bridge_dma_alias()
4271 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
4284 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices
4289 * host memory. These aliases mark the whole VCA device as one IOMMU
4293 * what slot is used on other side. This quirk is intended for both host
4319 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; in quirk_bridge_cavm_thrx2_pcie_root()
4327 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
4332 u32 class = pdev->class; in quirk_tw686x_class()
4335 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; in quirk_tw686x_class()
4336 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", in quirk_tw686x_class()
4337 class, pdev->class); in quirk_tw686x_class()
4355 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; in quirk_relaxedordering_disable()
4426 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4442 * If a non-compliant device generates a completion with a different
4444 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4448 * If the non-compliant device generates completions with zero attributes
4470 dev_name(&pdev->dev)); in quirk_disable_root_port_attributes()
4485 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely in quirk_chelsio_T5_disable_root_port_attributes()
4488 if ((pdev->device & 0xff00) == 0x5400) in quirk_chelsio_T5_disable_root_port_attributes()
4495 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided
4513 * AMD has indicated that the devices below do not support peer-to-peer
4516 * peer-to-peer between functions can claim to support a subset of ACS.
4528 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4529 * 1002:4384 SBx00 PCI to PCI Bridge
4534 * 1022:780f [AMD] FCH PCI Bridge
4544 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) in pci_quirk_amd_sb_acs()
4545 return -ENODEV; in pci_quirk_amd_sb_acs()
4550 return -ENODEV; in pci_quirk_amd_sb_acs()
4559 return -ENODEV; in pci_quirk_amd_sb_acs()
4568 switch (dev->device) { in pci_quirk_cavium_acs_match()
4585 return -ENOTTY; in pci_quirk_cavium_acs()
4602 * X-Gene Root Ports matching this quirk do not allow peer-to-peer in pci_quirk_xgene_acs()
4612 * But the implementation could block peer-to-peer transactions between them
4613 * and provide ACS-like functionality.
4620 return -ENOTTY; in pci_quirk_zhaoxin_pcie_ports_acs()
4626 switch (dev->device) { in pci_quirk_zhaoxin_pcie_ports_acs()
4638 * Many Intel PCH Root Ports do provide ACS-like features to disable peer
4653 /* Lynxpoint-H PCH */
4656 /* Lynxpoint-LP PCH */
4675 /* Filter out a few obvious non-matches first */ in pci_quirk_intel_pch_acs_match()
4680 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) in pci_quirk_intel_pch_acs_match()
4689 return -ENOTTY; in pci_quirk_intel_pch_acs()
4691 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) in pci_quirk_intel_pch_acs()
4699 * These QCOM Root Ports do provide ACS-like features to disable peer
4703 * Hardware doesn't support peer-to-peer and each Root Port is a Root
4729 return -ENOTTY; in pci_quirk_al_acs()
4733 * but do include ACS-like functionality. The hardware doesn't support in pci_quirk_al_acs()
4734 * peer-to-peer transactions via the root port and each has a unique in pci_quirk_al_acs()
4751 * dword accesses to them. This applies to the following PCI Device IDs, as
4754 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4755 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4763 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4764 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4767 * 0xa290-0xa29f PCI Express Root port #{0-16}
4768 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4774 * August 2017, Revision 002, Document#: 334660-002)[6]
4777 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4779 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4781 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4782 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
4783 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4784 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4785 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
4786 …ww.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-…
4787 …tel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datas…
4794 switch (dev->device) { in pci_quirk_intel_spt_pch_acs_match()
4812 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4814 pos = dev->acs_cap; in pci_quirk_intel_spt_pch_acs()
4816 return -ENOTTY; in pci_quirk_intel_spt_pch_acs()
4833 * in their ACS capability if they support peer-to-peer transactions. in pci_quirk_mf_endpoint_acs()
4835 * perform peer-to-peer with other functions, allowing us to mask out in pci_quirk_mf_endpoint_acs()
4847 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, in pci_quirk_rciep_acs()
4848 * "Root-Complex Peer to Peer Considerations". in pci_quirk_rciep_acs()
4851 return -ENOTTY; in pci_quirk_rciep_acs()
4861 * they do not allow peer-to-peer transactions between Root Ports. in pci_quirk_brcm_acs()
4870 * Wangxun 10G/1G NICs have no ACS capability, and on multi-function
4871 * devices, peer-to-peer transactions are not be used between the functions.
4878 switch (dev->device) { in pci_quirk_wangxun_nic_acs()
4951 /* 82571 (Quads omitted due to non-ACS switch) */
4968 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4969 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
4972 /* Cavium multi-function devices */
4976 /* APM X-Gene */
4987 /* Broadcom multi-function device */
4995 /* Zhaoxin multi-function devices */
5000 /* LX2xx0A : without security features + CAN-FD */
5004 /* LX2xx0C : security features + CAN-FD */
5016 /* LX2xx2A : without security features + CAN-FD */
5020 /* LX2xx2C : security features + CAN-FD */
5040 * pci_dev_specific_acs_enabled - check whether device provides ACS controls
5041 * @dev: PCI device
5045 * -ENOTTY: No quirk applies to this device; we can't tell whether the
5057 * or control to indicate their support here. Multi-function express in pci_dev_specific_acs_enabled()
5058 * devices which do not allow internal peer-to-peer between functions, in pci_dev_specific_acs_enabled()
5061 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { in pci_dev_specific_acs_enabled()
5062 if ((i->vendor == dev->vendor || in pci_dev_specific_acs_enabled()
5063 i->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_acs_enabled()
5064 (i->device == dev->device || in pci_dev_specific_acs_enabled()
5065 i->device == (u16)PCI_ANY_ID)) { in pci_dev_specific_acs_enabled()
5066 ret = i->acs_enabled(dev, acs_flags); in pci_dev_specific_acs_enabled()
5072 return -ENOTTY; in pci_dev_specific_acs_enabled()
5084 /* Backbone Peer Non-Posted Disable */
5104 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), in pci_quirk_enable_intel_lpc_acs()
5107 return -EINVAL; in pci_quirk_enable_intel_lpc_acs()
5112 return -ENOMEM; in pci_quirk_enable_intel_lpc_acs()
5116 * therefore read-only. If both posted and non-posted peer cycles are in pci_quirk_enable_intel_lpc_acs()
5147 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which in pci_quirk_enable_intel_rp_mpc_acs()
5164 * if dev->external_facing || dev->untrusted
5169 return -ENOTTY; in pci_quirk_enable_intel_pch_acs()
5178 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; in pci_quirk_enable_intel_pch_acs()
5191 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5193 pos = dev->acs_cap; in pci_quirk_enable_intel_spt_pch_acs()
5195 return -ENOTTY; in pci_quirk_enable_intel_spt_pch_acs()
5205 if (dev->external_facing || dev->untrusted) in pci_quirk_enable_intel_spt_pch_acs()
5221 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5223 pos = dev->acs_cap; in pci_quirk_disable_intel_spt_pch_acs_redir()
5225 return -ENOTTY; in pci_quirk_disable_intel_spt_pch_acs_redir()
5261 if ((p->vendor == dev->vendor || in pci_dev_specific_enable_acs()
5262 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5263 (p->device == dev->device || in pci_dev_specific_enable_acs()
5264 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_enable_acs()
5265 p->enable_acs) { in pci_dev_specific_enable_acs()
5266 ret = p->enable_acs(dev); in pci_dev_specific_enable_acs()
5272 return -ENOTTY; in pci_dev_specific_enable_acs()
5282 if ((p->vendor == dev->vendor || in pci_dev_specific_disable_acs_redir()
5283 p->vendor == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5284 (p->device == dev->device || in pci_dev_specific_disable_acs_redir()
5285 p->device == (u16)PCI_ANY_ID) && in pci_dev_specific_disable_acs_redir()
5286 p->disable_acs_redir) { in pci_dev_specific_disable_acs_redir()
5287 ret = p->disable_acs_redir(dev); in pci_dev_specific_disable_acs_redir()
5293 return -ENOTTY; in pci_dev_specific_disable_acs_redir()
5297 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with
5311 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) in quirk_intel_qat_vf_cap()
5331 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() in quirk_intel_qat_vf_cap()
5344 pdev->pcie_cap = pos; in quirk_intel_qat_vf_cap()
5346 pdev->pcie_flags_reg = reg16; in quirk_intel_qat_vf_cap()
5348 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; in quirk_intel_qat_vf_cap()
5350 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; in quirk_intel_qat_vf_cap()
5353 pdev->cfg_size = PCI_CFG_SPACE_SIZE; in quirk_intel_qat_vf_cap()
5363 state->cap.cap_nr = PCI_CAP_ID_EXP; in quirk_intel_qat_vf_cap()
5364 state->cap.cap_extended = 0; in quirk_intel_qat_vf_cap()
5365 state->cap.size = size; in quirk_intel_qat_vf_cap()
5366 cap = (u16 *)&state->cap.data[0]; in quirk_intel_qat_vf_cap()
5374 hlist_add_head(&state->next, &pdev->saved_cap_space); in quirk_intel_qat_vf_cap()
5383 * AMD Starship USB 3.0 Host Controller 0x148c
5384 * AMD Matisse USB 3.0 Host Controller 0x149c
5391 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; in quirk_no_flr()
5402 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); in quirk_no_ext_tags()
5407 bridge->no_ext_tags = 1; in quirk_no_ext_tags()
5410 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); in quirk_no_ext_tags()
5424 pdev->ats_cap = 0; in quirk_no_ats()
5434 if ((pdev->device == 0x7312 && pdev->revision != 0x00) || in quirk_amd_harvest_no_ats()
5435 (pdev->device == 0x7340 && pdev->revision != 0xc5) || in quirk_amd_harvest_no_ats()
5436 (pdev->device == 0x7341 && pdev->revision != 0x00)) in quirk_amd_harvest_no_ats()
5458 if (pdev->revision < 0x20) in quirk_intel_e2000_no_ats()
5476 pdev->no_msi = 1; in quirk_fsl_no_msi()
5481 * Although not allowed by the spec, some multi-function devices have
5494 if (PCI_FUNC(pdev->devfn) != consumer) in pci_create_device_link()
5497 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), in pci_create_device_link()
5498 pdev->bus->number, in pci_create_device_link()
5499 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); in pci_create_device_link()
5500 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { in pci_create_device_link()
5505 if (device_link_add(&pdev->dev, &supplier_pdev->dev, in pci_create_device_link()
5513 pm_runtime_allow(&pdev->dev); in pci_create_device_link()
5533 * Create device link for GPUs with integrated USB xHCI Host
5546 * Create device link for GPUs with integrated Type-C UCSI controller
5547 * to VGA. Currently there is no class code defined for UCSI device over PCI
5549 * over PCI gets a class code.
5573 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) in quirk_nvidia_hda()
5584 /* The GPU becomes a multi-function device when the HDA is enabled */ in quirk_nvidia_hda()
5586 gpu->multifunction = !!(hdr_type & 0x80); in quirk_nvidia_hda()
5597 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36:
5599 * Item #36 - Downstream port applies ACS Source Validation to Completions
5600 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that
5612 * write, so we do config reads until we receive a non-Config Request Retry
5623 struct pci_dev *bridge = bus->self; in pci_idt_bus_quirk()
5625 pos = bridge->acs_cap; in pci_idt_bus_quirk()
5637 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ in pci_idt_bus_quirk()
5641 /* Re-enable ACS_SV if it was previously enabled */ in pci_idt_bus_quirk()
5651 * originating requestor ID TLPs which access host memory on peer NTB
5681 partition = ioread8(&mmio_ntb->partition_id); in quirk_switchtec_ntb_dma_alias()
5683 partition_map = ioread32(&mmio_ntb->ep_map); in quirk_switchtec_ntb_dma_alias()
5684 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; in quirk_switchtec_ntb_dma_alias()
5699 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); in quirk_switchtec_ntb_dma_alias()
5716 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); in quirk_switchtec_ntb_dma_alias()
5817 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5818 pdev->subsystem_device != 0x222e || in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5819 !pdev->reset_fn) in quirk_reset_lenovo_thinkpad_p50_nvgpu()
5861 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); in pci_fixup_no_d0_pme()
5873 * 7.3.27, 7.3.29-7.3.31.
5879 dev->no_msi = 1; in pci_fixup_no_msi_no_pme()
5882 dev->pme_support = 0; in pci_fixup_no_msi_no_pme()
5889 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; in apex_pci_fixup_class()
5896 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; in nvidia_ion_ahci_fixup()