Lines Matching +full:pwm +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
31 #include <linux/pwm.h>
34 /* The following is global registers for PWM controller */
42 /* The following register is PWM channel related registers */
52 /* The following registers for PWM v1 */
57 /* The following registers for PWM v2 */
98 unsigned long offset) in atmel_pwm_readl() argument
100 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
104 unsigned long offset, unsigned long val) in atmel_pwm_writel() argument
106 writel_relaxed(val, chip->base + offset); in atmel_pwm_writel()
110 unsigned int ch, unsigned long offset) in atmel_pwm_ch_readl() argument
114 return atmel_pwm_readl(chip, base + offset); in atmel_pwm_ch_readl()
118 unsigned int ch, unsigned long offset, in atmel_pwm_ch_writel() argument
123 atmel_pwm_writel(chip, base + offset, val); in atmel_pwm_ch_writel()
131 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres()
135 cycles *= clk_get_rate(atmel_pwm->clk); in atmel_pwm_calculate_cprd_and_pres()
143 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
146 dev_err(chip->dev, "pres exceeds the maximum value\n"); in atmel_pwm_calculate_cprd_and_pres()
147 return -EINVAL; in atmel_pwm_calculate_cprd_and_pres()
163 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty()
166 do_div(cycles, state->period); in atmel_pwm_calculate_cdty()
167 *cdty = cprd - cycles; in atmel_pwm_calculate_cdty()
170 static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_update_cdty() argument
176 if (atmel_pwm->data->regs.duty_upd == in atmel_pwm_update_cdty()
177 atmel_pwm->data->regs.period_upd) { in atmel_pwm_update_cdty()
178 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_update_cdty()
180 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_update_cdty()
183 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_update_cdty()
184 atmel_pwm->data->regs.duty_upd, cdty); in atmel_pwm_update_cdty()
188 struct pwm_device *pwm, in atmel_pwm_set_cprd_cdty() argument
193 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
194 atmel_pwm->data->regs.duty, cdty); in atmel_pwm_set_cprd_cdty()
195 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, in atmel_pwm_set_cprd_cdty()
196 atmel_pwm->data->regs.period, cprd); in atmel_pwm_set_cprd_cdty()
199 static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_disable() argument
209 mutex_lock(&atmel_pwm->isr_lock); in atmel_pwm_disable()
210 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); in atmel_pwm_disable()
212 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
215 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); in atmel_pwm_disable()
218 mutex_unlock(&atmel_pwm->isr_lock); in atmel_pwm_disable()
219 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm); in atmel_pwm_disable()
222 * Wait for the PWM channel disable operation to be effective before in atmel_pwm_disable()
227 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) && in atmel_pwm_disable()
232 clk_disable(atmel_pwm->clk); in atmel_pwm_disable()
235 static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_apply() argument
244 pwm_get_state(pwm, &cstate); in atmel_pwm_apply()
246 if (state->enabled) { in atmel_pwm_apply()
248 cstate.polarity == state->polarity && in atmel_pwm_apply()
249 cstate.period == state->period) { in atmel_pwm_apply()
250 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_apply()
251 atmel_pwm->data->regs.period); in atmel_pwm_apply()
253 atmel_pwm_update_cdty(chip, pwm, cdty); in atmel_pwm_apply()
260 dev_err(chip->dev, in atmel_pwm_apply()
268 atmel_pwm_disable(chip, pwm, false); in atmel_pwm_apply()
270 ret = clk_enable(atmel_pwm->clk); in atmel_pwm_apply()
272 dev_err(chip->dev, "failed to enable clock\n"); in atmel_pwm_apply()
278 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_apply()
280 if (state->polarity == PWM_POLARITY_NORMAL) in atmel_pwm_apply()
284 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val); in atmel_pwm_apply()
285 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty); in atmel_pwm_apply()
286 mutex_lock(&atmel_pwm->isr_lock); in atmel_pwm_apply()
287 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR); in atmel_pwm_apply()
288 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm); in atmel_pwm_apply()
289 mutex_unlock(&atmel_pwm->isr_lock); in atmel_pwm_apply()
290 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm); in atmel_pwm_apply()
292 atmel_pwm_disable(chip, pwm, true); in atmel_pwm_apply()
298 static void atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in atmel_pwm_get_state() argument
305 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR); in atmel_pwm_get_state()
307 if (sr & (1 << pwm->hwpwm)) { in atmel_pwm_get_state()
308 unsigned long rate = clk_get_rate(atmel_pwm->clk); in atmel_pwm_get_state()
314 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_get_state()
315 atmel_pwm->data->regs.period); in atmel_pwm_get_state()
318 state->period = DIV64_U64_ROUND_UP(tmp, rate); in atmel_pwm_get_state()
320 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, in atmel_pwm_get_state()
321 atmel_pwm->data->regs.duty); in atmel_pwm_get_state()
322 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC; in atmel_pwm_get_state()
324 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate); in atmel_pwm_get_state()
326 state->enabled = true; in atmel_pwm_get_state()
328 state->enabled = false; in atmel_pwm_get_state()
332 state->polarity = PWM_POLARITY_INVERSED; in atmel_pwm_get_state()
334 state->polarity = PWM_POLARITY_NORMAL; in atmel_pwm_get_state()
384 .compatible = "atmel,at91sam9rl-pwm",
387 .compatible = "atmel,sama5d3-pwm",
390 .compatible = "atmel,sama5d2-pwm",
393 .compatible = "microchip,sam9x60-pwm",
407 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL); in atmel_pwm_probe()
409 return -ENOMEM; in atmel_pwm_probe()
411 mutex_init(&atmel_pwm->isr_lock); in atmel_pwm_probe()
412 atmel_pwm->data = of_device_get_match_data(&pdev->dev); in atmel_pwm_probe()
413 atmel_pwm->updated_pwms = 0; in atmel_pwm_probe()
416 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res); in atmel_pwm_probe()
417 if (IS_ERR(atmel_pwm->base)) in atmel_pwm_probe()
418 return PTR_ERR(atmel_pwm->base); in atmel_pwm_probe()
420 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL); in atmel_pwm_probe()
421 if (IS_ERR(atmel_pwm->clk)) in atmel_pwm_probe()
422 return PTR_ERR(atmel_pwm->clk); in atmel_pwm_probe()
424 ret = clk_prepare(atmel_pwm->clk); in atmel_pwm_probe()
426 dev_err(&pdev->dev, "failed to prepare PWM clock\n"); in atmel_pwm_probe()
430 atmel_pwm->chip.dev = &pdev->dev; in atmel_pwm_probe()
431 atmel_pwm->chip.ops = &atmel_pwm_ops; in atmel_pwm_probe()
432 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags; in atmel_pwm_probe()
433 atmel_pwm->chip.of_pwm_n_cells = 3; in atmel_pwm_probe()
434 atmel_pwm->chip.base = -1; in atmel_pwm_probe()
435 atmel_pwm->chip.npwm = 4; in atmel_pwm_probe()
437 ret = pwmchip_add(&atmel_pwm->chip); in atmel_pwm_probe()
439 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret); in atmel_pwm_probe()
448 clk_unprepare(atmel_pwm->clk); in atmel_pwm_probe()
456 clk_unprepare(atmel_pwm->clk); in atmel_pwm_remove()
457 mutex_destroy(&atmel_pwm->isr_lock); in atmel_pwm_remove()
459 return pwmchip_remove(&atmel_pwm->chip); in atmel_pwm_remove()
464 .name = "atmel-pwm",
472 MODULE_ALIAS("platform:atmel-pwm");
474 MODULE_DESCRIPTION("Atmel PWM driver");