Lines Matching +full:meson +full:- +full:gxbb +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * PWM controller driver for Amlogic Meson SoCs.
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
33 #include <linux/clk-provider.h>
42 #include <linux/pwm.h>
120 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in meson_pwm_request() argument
122 struct meson_pwm *meson = to_meson_pwm(chip); in meson_pwm_request() local
124 struct device *dev = chip->dev; in meson_pwm_request()
127 channel = pwm_get_chip_data(pwm); in meson_pwm_request()
131 channel = &meson->channels[pwm->hwpwm]; in meson_pwm_request()
133 if (channel->clk_parent) { in meson_pwm_request()
134 err = clk_set_parent(channel->clk, channel->clk_parent); in meson_pwm_request()
137 __clk_get_name(channel->clk_parent), in meson_pwm_request()
138 __clk_get_name(channel->clk), err); in meson_pwm_request()
143 err = clk_prepare_enable(channel->clk); in meson_pwm_request()
146 __clk_get_name(channel->clk), err); in meson_pwm_request()
153 static void meson_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in meson_pwm_free() argument
155 struct meson_pwm *meson = to_meson_pwm(chip); in meson_pwm_free() local
156 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_free()
159 clk_disable_unprepare(channel->clk); in meson_pwm_free()
162 static int meson_pwm_calc(struct meson_pwm *meson, struct pwm_device *pwm, in meson_pwm_calc() argument
165 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_calc()
170 duty = state->duty_cycle; in meson_pwm_calc()
171 period = state->period; in meson_pwm_calc()
179 if (state->polarity == PWM_POLARITY_INVERSED) in meson_pwm_calc()
180 duty = period - duty; in meson_pwm_calc()
182 fin_freq = clk_get_rate(channel->clk); in meson_pwm_calc()
184 dev_err(meson->chip.dev, "invalid source clock frequency\n"); in meson_pwm_calc()
185 return -EINVAL; in meson_pwm_calc()
188 dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); in meson_pwm_calc()
192 dev_err(meson->chip.dev, "unable to get period pre_div\n"); in meson_pwm_calc()
193 return -EINVAL; in meson_pwm_calc()
198 dev_err(meson->chip.dev, "unable to get period cnt\n"); in meson_pwm_calc()
199 return -EINVAL; in meson_pwm_calc()
202 dev_dbg(meson->chip.dev, "period=%llu pre_div=%u cnt=%u\n", period, in meson_pwm_calc()
206 channel->pre_div = pre_div; in meson_pwm_calc()
207 channel->hi = cnt; in meson_pwm_calc()
208 channel->lo = 0; in meson_pwm_calc()
210 channel->pre_div = pre_div; in meson_pwm_calc()
211 channel->hi = 0; in meson_pwm_calc()
212 channel->lo = cnt; in meson_pwm_calc()
217 dev_err(meson->chip.dev, "unable to get duty cycle\n"); in meson_pwm_calc()
218 return -EINVAL; in meson_pwm_calc()
221 dev_dbg(meson->chip.dev, "duty=%llu pre_div=%u duty_cnt=%u\n", in meson_pwm_calc()
224 channel->pre_div = pre_div; in meson_pwm_calc()
225 channel->hi = duty_cnt; in meson_pwm_calc()
226 channel->lo = cnt - duty_cnt; in meson_pwm_calc()
232 static void meson_pwm_enable(struct meson_pwm *meson, struct pwm_device *pwm) in meson_pwm_enable() argument
234 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_enable()
239 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; in meson_pwm_enable()
241 spin_lock_irqsave(&meson->lock, flags); in meson_pwm_enable()
243 value = readl(meson->base + REG_MISC_AB); in meson_pwm_enable()
244 value &= ~(MISC_CLK_DIV_MASK << channel_data->clk_div_shift); in meson_pwm_enable()
245 value |= channel->pre_div << channel_data->clk_div_shift; in meson_pwm_enable()
246 value |= channel_data->clk_en_mask; in meson_pwm_enable()
247 writel(value, meson->base + REG_MISC_AB); in meson_pwm_enable()
249 value = FIELD_PREP(PWM_HIGH_MASK, channel->hi) | in meson_pwm_enable()
250 FIELD_PREP(PWM_LOW_MASK, channel->lo); in meson_pwm_enable()
251 writel(value, meson->base + channel_data->reg_offset); in meson_pwm_enable()
253 value = readl(meson->base + REG_MISC_AB); in meson_pwm_enable()
254 value |= channel_data->pwm_en_mask; in meson_pwm_enable()
255 writel(value, meson->base + REG_MISC_AB); in meson_pwm_enable()
257 spin_unlock_irqrestore(&meson->lock, flags); in meson_pwm_enable()
260 static void meson_pwm_disable(struct meson_pwm *meson, struct pwm_device *pwm) in meson_pwm_disable() argument
265 spin_lock_irqsave(&meson->lock, flags); in meson_pwm_disable()
267 value = readl(meson->base + REG_MISC_AB); in meson_pwm_disable()
268 value &= ~meson_pwm_per_channel_data[pwm->hwpwm].pwm_en_mask; in meson_pwm_disable()
269 writel(value, meson->base + REG_MISC_AB); in meson_pwm_disable()
271 spin_unlock_irqrestore(&meson->lock, flags); in meson_pwm_disable()
274 static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in meson_pwm_apply() argument
277 struct meson_pwm *meson = to_meson_pwm(chip); in meson_pwm_apply() local
278 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_apply()
282 return -EINVAL; in meson_pwm_apply()
284 if (!state->enabled) { in meson_pwm_apply()
285 if (state->polarity == PWM_POLARITY_INVERSED) { in meson_pwm_apply()
298 channel->pre_div = 0; in meson_pwm_apply()
299 channel->hi = ~0; in meson_pwm_apply()
300 channel->lo = 0; in meson_pwm_apply()
302 meson_pwm_enable(meson, pwm); in meson_pwm_apply()
304 meson_pwm_disable(meson, pwm); in meson_pwm_apply()
307 err = meson_pwm_calc(meson, pwm, state); in meson_pwm_apply()
311 meson_pwm_enable(meson, pwm); in meson_pwm_apply()
318 struct pwm_device *pwm, u32 cnt) in meson_pwm_cnt_to_ns() argument
320 struct meson_pwm *meson = to_meson_pwm(chip); in meson_pwm_cnt_to_ns() local
326 channel = &meson->channels[pwm->hwpwm]; in meson_pwm_cnt_to_ns()
328 fin_freq = clk_get_rate(channel->clk); in meson_pwm_cnt_to_ns()
334 return cnt * fin_ns * (channel->pre_div + 1); in meson_pwm_cnt_to_ns()
337 static void meson_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in meson_pwm_get_state() argument
340 struct meson_pwm *meson = to_meson_pwm(chip); in meson_pwm_get_state() local
348 channel = &meson->channels[pwm->hwpwm]; in meson_pwm_get_state()
349 channel_data = &meson_pwm_per_channel_data[pwm->hwpwm]; in meson_pwm_get_state()
351 value = readl(meson->base + REG_MISC_AB); in meson_pwm_get_state()
353 tmp = channel_data->pwm_en_mask | channel_data->clk_en_mask; in meson_pwm_get_state()
354 state->enabled = (value & tmp) == tmp; in meson_pwm_get_state()
356 tmp = value >> channel_data->clk_div_shift; in meson_pwm_get_state()
357 channel->pre_div = FIELD_GET(MISC_CLK_DIV_MASK, tmp); in meson_pwm_get_state()
359 value = readl(meson->base + channel_data->reg_offset); in meson_pwm_get_state()
361 channel->lo = FIELD_GET(PWM_LOW_MASK, value); in meson_pwm_get_state()
362 channel->hi = FIELD_GET(PWM_HIGH_MASK, value); in meson_pwm_get_state()
364 if (channel->lo == 0) { in meson_pwm_get_state()
365 state->period = meson_pwm_cnt_to_ns(chip, pwm, channel->hi); in meson_pwm_get_state()
366 state->duty_cycle = state->period; in meson_pwm_get_state()
367 } else if (channel->lo >= channel->hi) { in meson_pwm_get_state()
368 state->period = meson_pwm_cnt_to_ns(chip, pwm, in meson_pwm_get_state()
369 channel->lo + channel->hi); in meson_pwm_get_state()
370 state->duty_cycle = meson_pwm_cnt_to_ns(chip, pwm, in meson_pwm_get_state()
371 channel->hi); in meson_pwm_get_state()
373 state->period = 0; in meson_pwm_get_state()
374 state->duty_cycle = 0; in meson_pwm_get_state()
376 state->polarity = PWM_POLARITY_NORMAL; in meson_pwm_get_state()
406 * Only the 2 first inputs of the GXBB AO PWMs are valid
465 .compatible = "amlogic,meson8b-pwm",
469 .compatible = "amlogic,meson-gxbb-pwm",
473 .compatible = "amlogic,meson-gxbb-ao-pwm",
477 .compatible = "amlogic,meson-axg-ee-pwm",
481 .compatible = "amlogic,meson-axg-ao-pwm",
485 .compatible = "amlogic,meson-g12a-ee-pwm",
489 .compatible = "amlogic,meson-g12a-ao-pwm-ab",
493 .compatible = "amlogic,meson-g12a-ao-pwm-cd",
500 static int meson_pwm_init_channels(struct meson_pwm *meson) in meson_pwm_init_channels() argument
502 struct device *dev = meson->chip.dev; in meson_pwm_init_channels()
508 for (i = 0; i < meson->chip.npwm; i++) { in meson_pwm_init_channels()
509 struct meson_pwm_channel *channel = &meson->channels[i]; in meson_pwm_init_channels()
516 init.parent_names = meson->data->parent_names; in meson_pwm_init_channels()
517 init.num_parents = meson->data->num_parents; in meson_pwm_init_channels()
519 channel->mux.reg = meson->base + REG_MISC_AB; in meson_pwm_init_channels()
520 channel->mux.shift = in meson_pwm_init_channels()
522 channel->mux.mask = MISC_CLK_SEL_MASK; in meson_pwm_init_channels()
523 channel->mux.flags = 0; in meson_pwm_init_channels()
524 channel->mux.lock = &meson->lock; in meson_pwm_init_channels()
525 channel->mux.table = NULL; in meson_pwm_init_channels()
526 channel->mux.hw.init = &init; in meson_pwm_init_channels()
528 channel->clk = devm_clk_register(dev, &channel->mux.hw); in meson_pwm_init_channels()
529 if (IS_ERR(channel->clk)) { in meson_pwm_init_channels()
530 err = PTR_ERR(channel->clk); in meson_pwm_init_channels()
537 channel->clk_parent = devm_clk_get_optional(dev, name); in meson_pwm_init_channels()
538 if (IS_ERR(channel->clk_parent)) in meson_pwm_init_channels()
539 return PTR_ERR(channel->clk_parent); in meson_pwm_init_channels()
547 struct meson_pwm *meson; in meson_pwm_probe() local
551 meson = devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); in meson_pwm_probe()
552 if (!meson) in meson_pwm_probe()
553 return -ENOMEM; in meson_pwm_probe()
556 meson->base = devm_ioremap_resource(&pdev->dev, regs); in meson_pwm_probe()
557 if (IS_ERR(meson->base)) in meson_pwm_probe()
558 return PTR_ERR(meson->base); in meson_pwm_probe()
560 spin_lock_init(&meson->lock); in meson_pwm_probe()
561 meson->chip.dev = &pdev->dev; in meson_pwm_probe()
562 meson->chip.ops = &meson_pwm_ops; in meson_pwm_probe()
563 meson->chip.base = -1; in meson_pwm_probe()
564 meson->chip.npwm = MESON_NUM_PWMS; in meson_pwm_probe()
565 meson->chip.of_xlate = of_pwm_xlate_with_flags; in meson_pwm_probe()
566 meson->chip.of_pwm_n_cells = 3; in meson_pwm_probe()
568 meson->data = of_device_get_match_data(&pdev->dev); in meson_pwm_probe()
570 err = meson_pwm_init_channels(meson); in meson_pwm_probe()
574 err = pwmchip_add(&meson->chip); in meson_pwm_probe()
576 dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); in meson_pwm_probe()
580 platform_set_drvdata(pdev, meson); in meson_pwm_probe()
587 struct meson_pwm *meson = platform_get_drvdata(pdev); in meson_pwm_remove() local
589 return pwmchip_remove(&meson->chip); in meson_pwm_remove()
594 .name = "meson-pwm",
602 MODULE_DESCRIPTION("Amlogic Meson PWM Generator driver");