Lines Matching +full:spi +full:- +full:tx +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
14 #include <linux/platform_data/dma-dw.h>
15 #include <linux/spi/spi.h>
18 #include "spi-dw.h"
29 if (s->dma_dev != chan->device->dev) in dw_spi_dma_chan_filter()
32 chan->private = s; in dw_spi_dma_chan_filter()
42 def_burst = dws->fifo_len / 2; in dw_spi_dma_maxburst_init()
44 ret = dma_get_slave_caps(dws->rxchan, &caps); in dw_spi_dma_maxburst_init()
50 dws->rxburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
51 dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); in dw_spi_dma_maxburst_init()
53 ret = dma_get_slave_caps(dws->txchan, &caps); in dw_spi_dma_maxburst_init()
60 * Having a Rx DMA channel serviced with higher priority than a Tx DMA in dw_spi_dma_maxburst_init()
61 * channel might not be enough to provide a well balanced DMA-based in dw_spi_dma_maxburst_init()
62 * SPI transfer interface. There might still be moments when the Tx DMA in dw_spi_dma_maxburst_init()
64 * That in its turn will eventually cause the SPI Rx FIFO overflow if in dw_spi_dma_maxburst_init()
65 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's in dw_spi_dma_maxburst_init()
66 * cleared by the Rx DMA channel. In order to fix the problem the Tx in dw_spi_dma_maxburst_init()
67 * DMA activity is intentionally slowed down by limiting the SPI Tx in dw_spi_dma_maxburst_init()
68 * FIFO depth with a value twice bigger than the Tx burst length. in dw_spi_dma_maxburst_init()
70 dws->txburst = min(max_burst, def_burst); in dw_spi_dma_maxburst_init()
71 dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); in dw_spi_dma_maxburst_init()
76 struct dma_slave_caps tx = {0}, rx = {0}; in dw_spi_dma_sg_burst_init() local
78 dma_get_slave_caps(dws->txchan, &tx); in dw_spi_dma_sg_burst_init()
79 dma_get_slave_caps(dws->rxchan, &rx); in dw_spi_dma_sg_burst_init()
81 if (tx.max_sg_burst > 0 && rx.max_sg_burst > 0) in dw_spi_dma_sg_burst_init()
82 dws->dma_sg_burst = min(tx.max_sg_burst, rx.max_sg_burst); in dw_spi_dma_sg_burst_init()
83 else if (tx.max_sg_burst > 0) in dw_spi_dma_sg_burst_init()
84 dws->dma_sg_burst = tx.max_sg_burst; in dw_spi_dma_sg_burst_init()
86 dws->dma_sg_burst = rx.max_sg_burst; in dw_spi_dma_sg_burst_init()
88 dws->dma_sg_burst = 0; in dw_spi_dma_sg_burst_init()
93 struct dw_dma_slave dma_tx = { .dst_id = 1 }, *tx = &dma_tx; in dw_spi_dma_init_mfld() local
104 return -ENODEV; in dw_spi_dma_init_mfld()
110 rx->dma_dev = &dma_dev->dev; in dw_spi_dma_init_mfld()
111 dws->rxchan = dma_request_channel(mask, dw_spi_dma_chan_filter, rx); in dw_spi_dma_init_mfld()
112 if (!dws->rxchan) in dw_spi_dma_init_mfld()
115 /* 2. Init tx channel */ in dw_spi_dma_init_mfld()
116 tx->dma_dev = &dma_dev->dev; in dw_spi_dma_init_mfld()
117 dws->txchan = dma_request_channel(mask, dw_spi_dma_chan_filter, tx); in dw_spi_dma_init_mfld()
118 if (!dws->txchan) in dw_spi_dma_init_mfld()
121 dws->master->dma_rx = dws->rxchan; in dw_spi_dma_init_mfld()
122 dws->master->dma_tx = dws->txchan; in dw_spi_dma_init_mfld()
124 init_completion(&dws->dma_completion); in dw_spi_dma_init_mfld()
135 dma_release_channel(dws->rxchan); in dw_spi_dma_init_mfld()
136 dws->rxchan = NULL; in dw_spi_dma_init_mfld()
139 return -EBUSY; in dw_spi_dma_init_mfld()
144 dws->rxchan = dma_request_slave_channel(dev, "rx"); in dw_spi_dma_init_generic()
145 if (!dws->rxchan) in dw_spi_dma_init_generic()
146 return -ENODEV; in dw_spi_dma_init_generic()
148 dws->txchan = dma_request_slave_channel(dev, "tx"); in dw_spi_dma_init_generic()
149 if (!dws->txchan) { in dw_spi_dma_init_generic()
150 dma_release_channel(dws->rxchan); in dw_spi_dma_init_generic()
151 dws->rxchan = NULL; in dw_spi_dma_init_generic()
152 return -ENODEV; in dw_spi_dma_init_generic()
155 dws->master->dma_rx = dws->rxchan; in dw_spi_dma_init_generic()
156 dws->master->dma_tx = dws->txchan; in dw_spi_dma_init_generic()
158 init_completion(&dws->dma_completion); in dw_spi_dma_init_generic()
169 if (dws->txchan) { in dw_spi_dma_exit()
170 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_exit()
171 dma_release_channel(dws->txchan); in dw_spi_dma_exit()
174 if (dws->rxchan) { in dw_spi_dma_exit()
175 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_exit()
176 dma_release_channel(dws->rxchan); in dw_spi_dma_exit()
184 complete(&dws->dma_completion); in dw_spi_dma_transfer_handler()
190 struct spi_device *spi, struct spi_transfer *xfer) in dw_spi_can_dma() argument
194 return xfer->len > dws->fifo_len; in dw_spi_can_dma()
218 ms = wait_for_completion_timeout(&dws->dma_completion, in dw_spi_dma_wait()
222 dev_err(&dws->master->cur_msg->spi->dev, in dw_spi_dma_wait()
224 return -ETIMEDOUT; in dw_spi_dma_wait()
239 struct spi_delay delay; in dw_spi_dma_wait_tx_done() local
243 delay.unit = SPI_DELAY_UNIT_SCK; in dw_spi_dma_wait_tx_done()
244 delay.value = nents * dws->n_bytes * BITS_PER_BYTE; in dw_spi_dma_wait_tx_done()
246 while (dw_spi_dma_tx_busy(dws) && retry--) in dw_spi_dma_wait_tx_done()
247 spi_delay_exec(&delay, xfer); in dw_spi_dma_wait_tx_done()
250 dev_err(&dws->master->dev, "Tx hanged up\n"); in dw_spi_dma_wait_tx_done()
251 return -EIO; in dw_spi_dma_wait_tx_done()
258 * dws->dma_chan_busy is set before the dma transfer starts, callback for tx
265 clear_bit(TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_tx_done()
266 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_tx_done()
269 complete(&dws->dma_completion); in dw_spi_dma_tx_done()
278 txconf.dst_addr = dws->dma_addr; in dw_spi_dma_config_tx()
279 txconf.dst_maxburst = dws->txburst; in dw_spi_dma_config_tx()
281 txconf.dst_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_tx()
284 return dmaengine_slave_config(dws->txchan, &txconf); in dw_spi_dma_config_tx()
294 txdesc = dmaengine_prep_slave_sg(dws->txchan, sgl, nents, in dw_spi_dma_submit_tx()
298 return -ENOMEM; in dw_spi_dma_submit_tx()
300 txdesc->callback = dw_spi_dma_tx_done; in dw_spi_dma_submit_tx()
301 txdesc->callback_param = dws; in dw_spi_dma_submit_tx()
306 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_submit_tx()
310 set_bit(TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_tx()
323 struct spi_delay delay; in dw_spi_dma_wait_rx_done() local
324 unsigned long ns, us; in dw_spi_dma_wait_rx_done() local
337 ns = 4U * NSEC_PER_SEC / dws->max_freq * nents; in dw_spi_dma_wait_rx_done()
339 delay.unit = SPI_DELAY_UNIT_NSECS; in dw_spi_dma_wait_rx_done()
340 delay.value = ns; in dw_spi_dma_wait_rx_done()
342 us = DIV_ROUND_UP(ns, NSEC_PER_USEC); in dw_spi_dma_wait_rx_done()
343 delay.unit = SPI_DELAY_UNIT_USECS; in dw_spi_dma_wait_rx_done()
344 delay.value = clamp_val(us, 0, USHRT_MAX); in dw_spi_dma_wait_rx_done()
347 while (dw_spi_dma_rx_busy(dws) && retry--) in dw_spi_dma_wait_rx_done()
348 spi_delay_exec(&delay, NULL); in dw_spi_dma_wait_rx_done()
351 dev_err(&dws->master->dev, "Rx hanged up\n"); in dw_spi_dma_wait_rx_done()
352 return -EIO; in dw_spi_dma_wait_rx_done()
359 * dws->dma_chan_busy is set before the dma transfer starts, callback for rx
366 clear_bit(RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_rx_done()
367 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) in dw_spi_dma_rx_done()
370 complete(&dws->dma_completion); in dw_spi_dma_rx_done()
379 rxconf.src_addr = dws->dma_addr; in dw_spi_dma_config_rx()
380 rxconf.src_maxburst = dws->rxburst; in dw_spi_dma_config_rx()
382 rxconf.src_addr_width = dw_spi_dma_convert_width(dws->n_bytes); in dw_spi_dma_config_rx()
385 return dmaengine_slave_config(dws->rxchan, &rxconf); in dw_spi_dma_config_rx()
395 rxdesc = dmaengine_prep_slave_sg(dws->rxchan, sgl, nents, in dw_spi_dma_submit_rx()
399 return -ENOMEM; in dw_spi_dma_submit_rx()
401 rxdesc->callback = dw_spi_dma_rx_done; in dw_spi_dma_submit_rx()
402 rxdesc->callback_param = dws; in dw_spi_dma_submit_rx()
407 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_submit_rx()
411 set_bit(RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_submit_rx()
421 if (!xfer->tx_buf) in dw_spi_dma_setup()
422 return -EINVAL; in dw_spi_dma_setup()
429 if (xfer->rx_buf) { in dw_spi_dma_setup()
437 if (xfer->rx_buf) in dw_spi_dma_setup()
443 if (xfer->rx_buf) in dw_spi_dma_setup()
447 reinit_completion(&dws->dma_completion); in dw_spi_dma_setup()
449 dws->transfer_handler = dw_spi_dma_transfer_handler; in dw_spi_dma_setup()
459 /* Submit the DMA Tx transfer */ in dw_spi_dma_transfer_all()
460 ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents); in dw_spi_dma_transfer_all()
465 if (xfer->rx_buf) { in dw_spi_dma_transfer_all()
466 ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl, in dw_spi_dma_transfer_all()
467 xfer->rx_sg.nents); in dw_spi_dma_transfer_all()
471 /* rx must be started before tx due to spi instinct */ in dw_spi_dma_transfer_all()
472 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_all()
475 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_all()
477 ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz); in dw_spi_dma_transfer_all()
488 * likely work that around by performing the IRQ-based SG list entries
489 * resubmission. That might and will cause a problem if the DMA Tx channel is
490 * recharged and re-executed before the Rx DMA channel. Due to
491 * non-deterministic IRQ-handler execution latency the DMA Tx channel will
492 * start pushing data to the SPI bus before the Rx DMA channel is even
493 * reinitialized with the next inbound SG list entry. By doing so the DMA Tx
495 * the DMA Rx channel being recharged and re-executed will eventually be
499 * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs
502 * (though total length should match) let's virtually split the SG-lists to the
503 * set of DMA transfers, which length is a minimum of the ordered SG-entries
504 * lengths. An ASCII-sketch of the implemented algo is following:
505 * xfer->len
528 for (base = 0, len = 0; base < xfer->len; base += len) { in dw_spi_dma_transfer_one()
529 /* Fetch next Tx DMA data chunk */ in dw_spi_dma_transfer_one()
531 tx_sg = !tx_sg ? &xfer->tx_sg.sgl[0] : sg_next(tx_sg); in dw_spi_dma_transfer_one()
538 rx_sg = !rx_sg ? &xfer->rx_sg.sgl[0] : sg_next(rx_sg); in dw_spi_dma_transfer_one()
548 /* Submit DMA Tx transfer */ in dw_spi_dma_transfer_one()
558 /* Rx must be started before Tx due to SPI instinct */ in dw_spi_dma_transfer_one()
559 dma_async_issue_pending(dws->rxchan); in dw_spi_dma_transfer_one()
561 dma_async_issue_pending(dws->txchan); in dw_spi_dma_transfer_one()
565 * finished since SPI controller is kept enabled during the in dw_spi_dma_transfer_one()
567 * data left in the Tx/Rx FIFOs. in dw_spi_dma_transfer_one()
569 ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz); in dw_spi_dma_transfer_one()
573 reinit_completion(&dws->dma_completion); in dw_spi_dma_transfer_one()
577 tx_len -= len; in dw_spi_dma_transfer_one()
578 rx_len -= len; in dw_spi_dma_transfer_one()
591 nents = max(xfer->tx_sg.nents, xfer->rx_sg.nents); in dw_spi_dma_transfer()
594 * Execute normal DMA-based transfer (which submits the Rx and Tx SG in dw_spi_dma_transfer()
597 * Tx-only SPI transfer is requested, or the DMA engine is capable to in dw_spi_dma_transfer()
600 if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst) in dw_spi_dma_transfer()
607 if (dws->master->cur_msg->status == -EINPROGRESS) { in dw_spi_dma_transfer()
613 if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS) in dw_spi_dma_transfer()
621 if (test_bit(TX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
622 dmaengine_terminate_sync(dws->txchan); in dw_spi_dma_stop()
623 clear_bit(TX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
625 if (test_bit(RX_BUSY, &dws->dma_chan_busy)) { in dw_spi_dma_stop()
626 dmaengine_terminate_sync(dws->rxchan); in dw_spi_dma_stop()
627 clear_bit(RX_BUSY, &dws->dma_chan_busy); in dw_spi_dma_stop()
642 dws->dma_ops = &dw_spi_dma_mfld_ops; in dw_spi_dma_setup_mfld()
657 dws->dma_ops = &dw_spi_dma_generic_ops; in dw_spi_dma_setup_generic()