Lines Matching +full:spi +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <linux/platform_data/spi-mt65xx.h>
19 #include <linux/spi/spi.h>
20 #include <linux/dma-mapping.h>
96 void __iomem *base; member
147 { .compatible = "mediatek,mt2701-spi",
150 { .compatible = "mediatek,mt2712-spi",
153 { .compatible = "mediatek,mt6589-spi",
156 { .compatible = "mediatek,mt6765-spi",
159 { .compatible = "mediatek,mt7622-spi",
162 { .compatible = "mediatek,mt7629-spi",
165 { .compatible = "mediatek,mt8135-spi",
168 { .compatible = "mediatek,mt8173-spi",
171 { .compatible = "mediatek,mt8183-spi",
174 { .compatible = "mediatek,mt8192-spi",
186 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
188 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
190 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
192 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
200 struct spi_device *spi = msg->spi; in mtk_spi_prepare_message() local
201 struct mtk_chip_config *chip_config = spi->controller_data; in mtk_spi_prepare_message()
204 cpha = spi->mode & SPI_CPHA ? 1 : 0; in mtk_spi_prepare_message()
205 cpol = spi->mode & SPI_CPOL ? 1 : 0; in mtk_spi_prepare_message()
207 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
218 if (spi->mode & SPI_LSB_FIRST) { in mtk_spi_prepare_message()
235 if (mdata->dev_comp->enhance_timing) { in mtk_spi_prepare_message()
237 if (spi->mode & SPI_CS_HIGH) in mtk_spi_prepare_message()
242 if (chip_config->sample_sel) in mtk_spi_prepare_message()
257 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
260 if (mdata->dev_comp->need_pad_sel) in mtk_spi_prepare_message()
261 writel(mdata->pad_sel[spi->chip_select], in mtk_spi_prepare_message()
262 mdata->base + SPI_PAD_SEL_REG); in mtk_spi_prepare_message()
267 static void mtk_spi_set_cs(struct spi_device *spi, bool enable) in mtk_spi_set_cs() argument
270 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); in mtk_spi_set_cs()
272 if (spi->mode & SPI_CS_HIGH) in mtk_spi_set_cs()
275 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
278 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
281 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_set_cs()
282 mdata->state = MTK_SPI_IDLE; in mtk_spi_set_cs()
293 spi_clk_hz = clk_get_rate(mdata->spi_clk); in mtk_spi_prepare_transfer()
294 if (xfer->speed_hz < spi_clk_hz / 2) in mtk_spi_prepare_transfer()
295 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); in mtk_spi_prepare_transfer()
302 if (mdata->dev_comp->enhance_timing) { in mtk_spi_prepare_transfer()
303 reg_val = (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
305 reg_val |= (((sck_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
307 writel(reg_val, mdata->base + SPI_CFG2_REG); in mtk_spi_prepare_transfer()
308 reg_val = (((cs_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
310 reg_val |= (((cs_time - 1) & 0xffff) in mtk_spi_prepare_transfer()
312 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
314 reg_val = (((sck_time - 1) & 0xff) in mtk_spi_prepare_transfer()
316 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); in mtk_spi_prepare_transfer()
317 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); in mtk_spi_prepare_transfer()
318 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); in mtk_spi_prepare_transfer()
319 writel(reg_val, mdata->base + SPI_CFG0_REG); in mtk_spi_prepare_transfer()
322 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_prepare_transfer()
324 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); in mtk_spi_prepare_transfer()
325 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_prepare_transfer()
333 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); in mtk_spi_setup_packet()
334 packet_loop = mdata->xfer_len / packet_size; in mtk_spi_setup_packet()
336 reg_val = readl(mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
338 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; in mtk_spi_setup_packet()
339 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; in mtk_spi_setup_packet()
340 writel(reg_val, mdata->base + SPI_CFG1_REG); in mtk_spi_setup_packet()
348 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_enable_transfer()
349 if (mdata->state == MTK_SPI_IDLE) in mtk_spi_enable_transfer()
353 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_enable_transfer()
373 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
374 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
375 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); in mtk_spi_update_mdata_len()
376 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
377 mdata->rx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
378 mdata->tx_sgl_len -= mdata->xfer_len; in mtk_spi_update_mdata_len()
380 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); in mtk_spi_update_mdata_len()
381 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
382 mdata->tx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
383 mdata->rx_sgl_len -= mdata->xfer_len; in mtk_spi_update_mdata_len()
385 } else if (mdata->tx_sgl_len) { in mtk_spi_update_mdata_len()
386 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); in mtk_spi_update_mdata_len()
387 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
388 mdata->tx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
389 } else if (mdata->rx_sgl_len) { in mtk_spi_update_mdata_len()
390 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); in mtk_spi_update_mdata_len()
391 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; in mtk_spi_update_mdata_len()
392 mdata->rx_sgl_len = mult_delta; in mtk_spi_update_mdata_len()
401 if (mdata->tx_sgl) { in mtk_spi_setup_dma_addr()
402 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_setup_dma_addr()
403 mdata->base + SPI_TX_SRC_REG); in mtk_spi_setup_dma_addr()
405 if (mdata->dev_comp->dma_ext) in mtk_spi_setup_dma_addr()
406 writel((u32)(xfer->tx_dma >> 32), in mtk_spi_setup_dma_addr()
407 mdata->base + SPI_TX_SRC_REG_64); in mtk_spi_setup_dma_addr()
411 if (mdata->rx_sgl) { in mtk_spi_setup_dma_addr()
412 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), in mtk_spi_setup_dma_addr()
413 mdata->base + SPI_RX_DST_REG); in mtk_spi_setup_dma_addr()
415 if (mdata->dev_comp->dma_ext) in mtk_spi_setup_dma_addr()
416 writel((u32)(xfer->rx_dma >> 32), in mtk_spi_setup_dma_addr()
417 mdata->base + SPI_RX_DST_REG_64); in mtk_spi_setup_dma_addr()
423 struct spi_device *spi, in mtk_spi_fifo_transfer() argument
430 mdata->cur_transfer = xfer; in mtk_spi_fifo_transfer()
431 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); in mtk_spi_fifo_transfer()
432 mdata->num_xfered = 0; in mtk_spi_fifo_transfer()
436 if (xfer->tx_buf) { in mtk_spi_fifo_transfer()
437 cnt = xfer->len / 4; in mtk_spi_fifo_transfer()
438 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); in mtk_spi_fifo_transfer()
439 remainder = xfer->len % 4; in mtk_spi_fifo_transfer()
442 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); in mtk_spi_fifo_transfer()
443 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_fifo_transfer()
453 struct spi_device *spi, in mtk_spi_dma_transfer() argument
459 mdata->tx_sgl = NULL; in mtk_spi_dma_transfer()
460 mdata->rx_sgl = NULL; in mtk_spi_dma_transfer()
461 mdata->tx_sgl_len = 0; in mtk_spi_dma_transfer()
462 mdata->rx_sgl_len = 0; in mtk_spi_dma_transfer()
463 mdata->cur_transfer = xfer; in mtk_spi_dma_transfer()
464 mdata->num_xfered = 0; in mtk_spi_dma_transfer()
468 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_dma_transfer()
469 if (xfer->tx_buf) in mtk_spi_dma_transfer()
471 if (xfer->rx_buf) in mtk_spi_dma_transfer()
473 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_dma_transfer()
475 if (xfer->tx_buf) in mtk_spi_dma_transfer()
476 mdata->tx_sgl = xfer->tx_sg.sgl; in mtk_spi_dma_transfer()
477 if (xfer->rx_buf) in mtk_spi_dma_transfer()
478 mdata->rx_sgl = xfer->rx_sg.sgl; in mtk_spi_dma_transfer()
480 if (mdata->tx_sgl) { in mtk_spi_dma_transfer()
481 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); in mtk_spi_dma_transfer()
482 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); in mtk_spi_dma_transfer()
484 if (mdata->rx_sgl) { in mtk_spi_dma_transfer()
485 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); in mtk_spi_dma_transfer()
486 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); in mtk_spi_dma_transfer()
498 struct spi_device *spi, in mtk_spi_transfer_one() argument
501 if (master->can_dma(master, spi, xfer)) in mtk_spi_transfer_one()
502 return mtk_spi_dma_transfer(master, spi, xfer); in mtk_spi_transfer_one()
504 return mtk_spi_fifo_transfer(master, spi, xfer); in mtk_spi_transfer_one()
508 struct spi_device *spi, in mtk_spi_can_dma() argument
511 /* Buffers for DMA transactions must be 4-byte aligned */ in mtk_spi_can_dma()
512 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && in mtk_spi_can_dma()
513 (unsigned long)xfer->tx_buf % 4 == 0 && in mtk_spi_can_dma()
514 (unsigned long)xfer->rx_buf % 4 == 0); in mtk_spi_can_dma()
517 static int mtk_spi_setup(struct spi_device *spi) in mtk_spi_setup() argument
519 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); in mtk_spi_setup()
521 if (!spi->controller_data) in mtk_spi_setup()
522 spi->controller_data = (void *)&mtk_default_chip_info; in mtk_spi_setup()
524 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) in mtk_spi_setup()
525 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); in mtk_spi_setup()
535 struct spi_transfer *trans = mdata->cur_transfer; in mtk_spi_interrupt()
537 reg_val = readl(mdata->base + SPI_STATUS0_REG); in mtk_spi_interrupt()
539 mdata->state = MTK_SPI_PAUSED; in mtk_spi_interrupt()
541 mdata->state = MTK_SPI_IDLE; in mtk_spi_interrupt()
543 if (!master->can_dma(master, NULL, trans)) { in mtk_spi_interrupt()
544 if (trans->rx_buf) { in mtk_spi_interrupt()
545 cnt = mdata->xfer_len / 4; in mtk_spi_interrupt()
546 ioread32_rep(mdata->base + SPI_RX_DATA_REG, in mtk_spi_interrupt()
547 trans->rx_buf + mdata->num_xfered, cnt); in mtk_spi_interrupt()
548 remainder = mdata->xfer_len % 4; in mtk_spi_interrupt()
550 reg_val = readl(mdata->base + SPI_RX_DATA_REG); in mtk_spi_interrupt()
551 memcpy(trans->rx_buf + in mtk_spi_interrupt()
552 mdata->num_xfered + in mtk_spi_interrupt()
559 mdata->num_xfered += mdata->xfer_len; in mtk_spi_interrupt()
560 if (mdata->num_xfered == trans->len) { in mtk_spi_interrupt()
565 len = trans->len - mdata->num_xfered; in mtk_spi_interrupt()
566 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); in mtk_spi_interrupt()
569 cnt = mdata->xfer_len / 4; in mtk_spi_interrupt()
570 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, in mtk_spi_interrupt()
571 trans->tx_buf + mdata->num_xfered, cnt); in mtk_spi_interrupt()
573 remainder = mdata->xfer_len % 4; in mtk_spi_interrupt()
577 trans->tx_buf + (cnt * 4) + mdata->num_xfered, in mtk_spi_interrupt()
579 writel(reg_val, mdata->base + SPI_TX_DATA_REG); in mtk_spi_interrupt()
587 if (mdata->tx_sgl) in mtk_spi_interrupt()
588 trans->tx_dma += mdata->xfer_len; in mtk_spi_interrupt()
589 if (mdata->rx_sgl) in mtk_spi_interrupt()
590 trans->rx_dma += mdata->xfer_len; in mtk_spi_interrupt()
592 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { in mtk_spi_interrupt()
593 mdata->tx_sgl = sg_next(mdata->tx_sgl); in mtk_spi_interrupt()
594 if (mdata->tx_sgl) { in mtk_spi_interrupt()
595 trans->tx_dma = sg_dma_address(mdata->tx_sgl); in mtk_spi_interrupt()
596 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); in mtk_spi_interrupt()
599 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { in mtk_spi_interrupt()
600 mdata->rx_sgl = sg_next(mdata->rx_sgl); in mtk_spi_interrupt()
601 if (mdata->rx_sgl) { in mtk_spi_interrupt()
602 trans->rx_dma = sg_dma_address(mdata->rx_sgl); in mtk_spi_interrupt()
603 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); in mtk_spi_interrupt()
607 if (!mdata->tx_sgl && !mdata->rx_sgl) { in mtk_spi_interrupt()
608 /* spi disable dma */ in mtk_spi_interrupt()
609 cmd = readl(mdata->base + SPI_CMD_REG); in mtk_spi_interrupt()
612 writel(cmd, mdata->base + SPI_CMD_REG); in mtk_spi_interrupt()
633 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); in mtk_spi_probe()
635 dev_err(&pdev->dev, "failed to alloc spi master\n"); in mtk_spi_probe()
636 return -ENOMEM; in mtk_spi_probe()
639 master->auto_runtime_pm = true; in mtk_spi_probe()
640 master->dev.of_node = pdev->dev.of_node; in mtk_spi_probe()
641 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; in mtk_spi_probe()
643 master->set_cs = mtk_spi_set_cs; in mtk_spi_probe()
644 master->prepare_message = mtk_spi_prepare_message; in mtk_spi_probe()
645 master->transfer_one = mtk_spi_transfer_one; in mtk_spi_probe()
646 master->can_dma = mtk_spi_can_dma; in mtk_spi_probe()
647 master->setup = mtk_spi_setup; in mtk_spi_probe()
649 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); in mtk_spi_probe()
651 dev_err(&pdev->dev, "failed to probe of_node\n"); in mtk_spi_probe()
652 ret = -EINVAL; in mtk_spi_probe()
657 mdata->dev_comp = of_id->data; in mtk_spi_probe()
659 if (mdata->dev_comp->enhance_timing) in mtk_spi_probe()
660 master->mode_bits |= SPI_CS_HIGH; in mtk_spi_probe()
662 if (mdata->dev_comp->must_tx) in mtk_spi_probe()
663 master->flags = SPI_MASTER_MUST_TX; in mtk_spi_probe()
665 if (mdata->dev_comp->need_pad_sel) { in mtk_spi_probe()
666 mdata->pad_num = of_property_count_u32_elems( in mtk_spi_probe()
667 pdev->dev.of_node, in mtk_spi_probe()
668 "mediatek,pad-select"); in mtk_spi_probe()
669 if (mdata->pad_num < 0) { in mtk_spi_probe()
670 dev_err(&pdev->dev, in mtk_spi_probe()
671 "No 'mediatek,pad-select' property\n"); in mtk_spi_probe()
672 ret = -EINVAL; in mtk_spi_probe()
676 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, in mtk_spi_probe()
678 if (!mdata->pad_sel) { in mtk_spi_probe()
679 ret = -ENOMEM; in mtk_spi_probe()
683 for (i = 0; i < mdata->pad_num; i++) { in mtk_spi_probe()
684 of_property_read_u32_index(pdev->dev.of_node, in mtk_spi_probe()
685 "mediatek,pad-select", in mtk_spi_probe()
686 i, &mdata->pad_sel[i]); in mtk_spi_probe()
687 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { in mtk_spi_probe()
688 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", in mtk_spi_probe()
689 i, mdata->pad_sel[i]); in mtk_spi_probe()
690 ret = -EINVAL; in mtk_spi_probe()
697 mdata->base = devm_platform_ioremap_resource(pdev, 0); in mtk_spi_probe()
698 if (IS_ERR(mdata->base)) { in mtk_spi_probe()
699 ret = PTR_ERR(mdata->base); in mtk_spi_probe()
709 if (!pdev->dev.dma_mask) in mtk_spi_probe()
710 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; in mtk_spi_probe()
712 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, in mtk_spi_probe()
713 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); in mtk_spi_probe()
715 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); in mtk_spi_probe()
719 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); in mtk_spi_probe()
720 if (IS_ERR(mdata->parent_clk)) { in mtk_spi_probe()
721 ret = PTR_ERR(mdata->parent_clk); in mtk_spi_probe()
722 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); in mtk_spi_probe()
726 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); in mtk_spi_probe()
727 if (IS_ERR(mdata->sel_clk)) { in mtk_spi_probe()
728 ret = PTR_ERR(mdata->sel_clk); in mtk_spi_probe()
729 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); in mtk_spi_probe()
733 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); in mtk_spi_probe()
734 if (IS_ERR(mdata->spi_clk)) { in mtk_spi_probe()
735 ret = PTR_ERR(mdata->spi_clk); in mtk_spi_probe()
736 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); in mtk_spi_probe()
740 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_probe()
742 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); in mtk_spi_probe()
746 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); in mtk_spi_probe()
748 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); in mtk_spi_probe()
749 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_probe()
753 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_probe()
755 pm_runtime_enable(&pdev->dev); in mtk_spi_probe()
757 ret = devm_spi_register_master(&pdev->dev, master); in mtk_spi_probe()
759 dev_err(&pdev->dev, "failed to register master (%d)\n", ret); in mtk_spi_probe()
763 if (mdata->dev_comp->need_pad_sel) { in mtk_spi_probe()
764 if (mdata->pad_num != master->num_chipselect) { in mtk_spi_probe()
765 dev_err(&pdev->dev, in mtk_spi_probe()
767 mdata->pad_num, master->num_chipselect); in mtk_spi_probe()
768 ret = -EINVAL; in mtk_spi_probe()
772 if (!master->cs_gpios && master->num_chipselect > 1) { in mtk_spi_probe()
773 dev_err(&pdev->dev, in mtk_spi_probe()
775 ret = -EINVAL; in mtk_spi_probe()
779 if (master->cs_gpios) { in mtk_spi_probe()
780 for (i = 0; i < master->num_chipselect; i++) { in mtk_spi_probe()
781 ret = devm_gpio_request(&pdev->dev, in mtk_spi_probe()
782 master->cs_gpios[i], in mtk_spi_probe()
783 dev_name(&pdev->dev)); in mtk_spi_probe()
785 dev_err(&pdev->dev, in mtk_spi_probe()
793 if (mdata->dev_comp->dma_ext) in mtk_spi_probe()
797 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); in mtk_spi_probe()
799 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", in mtk_spi_probe()
805 pm_runtime_disable(&pdev->dev); in mtk_spi_probe()
817 pm_runtime_disable(&pdev->dev); in mtk_spi_remove()
836 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_suspend()
848 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_resume()
857 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_resume()
869 clk_disable_unprepare(mdata->spi_clk); in mtk_spi_runtime_suspend()
880 ret = clk_prepare_enable(mdata->spi_clk); in mtk_spi_runtime_resume()
898 .name = "mtk-spi",
908 MODULE_DESCRIPTION("MTK SPI Controller driver");
911 MODULE_ALIAS("platform:mtk-spi");