Lines Matching +full:reference +full:- +full:div +full:- +full:factor
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
137 * 00 -> 5 bit words
138 * 01 -> 6 bit words
139 * 10 -> 7 bit words
140 * 11 -> 8 bit words
145 * 0 -> 1 stop bit
146 * 1 -> 1-1.5 stop bits if
152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
184 * 00 -> no transmitter flow
186 * 01 -> receiver compares
190 * 10 -> receiver compares
194 * 11 -> receiver compares
203 * 00 -> no received flow
205 * 01 -> transmitter generates
207 * 10 -> transmitter generates
209 * 11 -> transmitter generates
216 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
238 /* Crystal-related definitions */
296 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_read()
299 regmap_read(s->regmap, port->iobase + reg, &val); in max310x_port_read()
306 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_write()
308 regmap_write(s->regmap, port->iobase + reg, val); in max310x_port_write()
313 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_port_update()
315 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); in max310x_port_update()
324 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); in max3107_detect()
330 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3107_detect()
331 return -ENODEV; in max3107_detect()
346 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); in max3108_detect()
351 dev_err(dev, "%s not present\n", s->devtype->name); in max3108_detect()
352 return -ENODEV; in max3108_detect()
364 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max3109_detect()
369 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); in max3109_detect()
370 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); in max3109_detect()
373 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max3109_detect()
374 return -ENODEV; in max3109_detect()
395 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, in max14830_detect()
400 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); in max14830_detect()
401 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); in max14830_detect()
404 "%s ID 0x%02x does not match\n", s->devtype->name, val); in max14830_detect()
405 return -ENODEV; in max14830_detect()
508 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; in max310x_set_baud() local
512 * in case if the requested baud is too high for the pre-defined in max310x_set_baud()
515 div = port->uartclk / baud; in max310x_set_baud()
516 if (div < 8) { in max310x_set_baud()
520 } else if (div < 16) { in max310x_set_baud()
529 div /= c; in max310x_set_baud()
533 if (div > 0) in max310x_set_baud()
534 frac = (16*(port->uartclk % F)) / F; in max310x_set_baud()
536 div = 1; in max310x_set_baud()
538 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); in max310x_set_baud()
539 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); in max310x_set_baud()
543 return (16*port->uartclk) / (c*(16*div + frac)); in max310x_set_baud()
562 unsigned int div, clksrc, pllcfg = 0; in max310x_set_ref_clk() local
563 long besterr = -1; in max310x_set_ref_clk()
570 for (div = 1; (div <= 63) && besterr; div++) { in max310x_set_ref_clk()
571 fdiv = DIV_ROUND_CLOSEST(freq, div); in max310x_set_ref_clk()
577 pllcfg = (0 << 6) | div; in max310x_set_ref_clk()
584 pllcfg = (1 << 6) | div; in max310x_set_ref_clk()
591 pllcfg = (2 << 6) | div; in max310x_set_ref_clk()
598 pllcfg = (3 << 6) | div; in max310x_set_ref_clk()
609 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); in max310x_set_ref_clk()
613 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); in max310x_set_ref_clk()
622 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); in max310x_set_ref_clk()
640 .tx_buf = &one->wr_header, in max310x_batch_write()
641 .len = sizeof(one->wr_header), in max310x_batch_write()
647 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); in max310x_batch_write()
655 .tx_buf = &one->rd_header, in max310x_batch_read()
656 .len = sizeof(one->rd_header), in max310x_batch_read()
662 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); in max310x_batch_read()
670 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { in max310x_handle_rx()
672 * Break condition, parity checking, framing errors -- they in max310x_handle_rx()
673 * are all ignored. That means that we can do a batch-read. in max310x_handle_rx()
683 max310x_batch_read(port, one->rx_buf, rxlen); in max310x_handle_rx()
685 port->icount.rx += rxlen; in max310x_handle_rx()
687 sts &= port->read_status_mask; in max310x_handle_rx()
690 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); in max310x_handle_rx()
691 port->icount.overrun++; in max310x_handle_rx()
694 for (i = 0; i < (rxlen - 1); ++i) in max310x_handle_rx()
695 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); in max310x_handle_rx()
703 one->rx_buf[rxlen-1], flag); in max310x_handle_rx()
706 if (unlikely(rxlen >= port->fifosize)) { in max310x_handle_rx()
707 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); in max310x_handle_rx()
708 port->icount.buf_overrun++; in max310x_handle_rx()
710 rxlen = port->fifosize; in max310x_handle_rx()
713 while (rxlen--) { in max310x_handle_rx()
720 port->icount.rx++; in max310x_handle_rx()
725 port->icount.brk++; in max310x_handle_rx()
729 port->icount.parity++; in max310x_handle_rx()
731 port->icount.frame++; in max310x_handle_rx()
733 port->icount.overrun++; in max310x_handle_rx()
735 sts &= port->read_status_mask; in max310x_handle_rx()
749 if (sts & port->ignore_status_mask) in max310x_handle_rx()
756 tty_flip_buffer_push(&port->state->port); in max310x_handle_rx()
761 struct circ_buf *xmit = &port->state->xmit; in max310x_handle_tx()
764 if (unlikely(port->x_char)) { in max310x_handle_tx()
765 max310x_port_write(port, MAX310X_THR_REG, port->x_char); in max310x_handle_tx()
766 port->icount.tx++; in max310x_handle_tx()
767 port->x_char = 0; in max310x_handle_tx()
776 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); in max310x_handle_tx()
780 txlen = port->fifosize - txlen; in max310x_handle_tx()
784 /* It's a circ buffer -- wrap around. in max310x_handle_tx()
786 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); in max310x_handle_tx()
787 max310x_batch_write(port, xmit->buf, to_send - until_end); in max310x_handle_tx()
789 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); in max310x_handle_tx()
793 port->icount.tx += to_send; in max310x_handle_tx()
794 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); in max310x_handle_tx()
805 schedule_work(&one->tx_work); in max310x_start_tx()
810 struct uart_port *port = &s->p[portno].port; in max310x_port_irq()
842 if (s->devtype->nr > 1) { in max310x_ist()
846 WARN_ON_ONCE(regmap_read(s->regmap, in max310x_ist()
848 val = ((1 << s->devtype->nr) - 1) & ~val; in max310x_ist()
851 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) in max310x_ist()
866 max310x_handle_tx(&one->port); in max310x_tx_proc()
888 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_md_proc()
890 (one->port.mctrl & TIOCM_LOOP) ? in max310x_md_proc()
898 schedule_work(&one->md_work); in max310x_set_mctrl()
916 termios->c_cflag &= ~CMSPAR; in max310x_set_termios()
919 switch (termios->c_cflag & CSIZE) { in max310x_set_termios()
935 if (termios->c_cflag & PARENB) { in max310x_set_termios()
937 if (!(termios->c_cflag & PARODD)) in max310x_set_termios()
942 if (termios->c_cflag & CSTOPB) in max310x_set_termios()
949 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; in max310x_set_termios()
950 if (termios->c_iflag & INPCK) in max310x_set_termios()
951 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
953 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in max310x_set_termios()
954 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
957 port->ignore_status_mask = 0; in max310x_set_termios()
958 if (termios->c_iflag & IGNBRK) in max310x_set_termios()
959 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; in max310x_set_termios()
960 if (!(termios->c_cflag & CREAD)) in max310x_set_termios()
961 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | in max310x_set_termios()
967 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); in max310x_set_termios()
968 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); in max310x_set_termios()
973 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { in max310x_set_termios()
979 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); in max310x_set_termios()
981 if (termios->c_cflag & CRTSCTS) { in max310x_set_termios()
983 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in max310x_set_termios()
987 if (termios->c_iflag & IXON) in max310x_set_termios()
990 if (termios->c_iflag & IXOFF) { in max310x_set_termios()
991 port->status |= UPSTAT_AUTOXOFF; in max310x_set_termios()
1000 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { in max310x_set_termios()
1008 port->uartclk / 16 / 0xffff, in max310x_set_termios()
1009 port->uartclk / 4); in max310x_set_termios()
1015 uart_update_timeout(port, termios->c_cflag, baud); in max310x_set_termios()
1023 delay = (one->port.rs485.delay_rts_before_send << 4) | in max310x_rs_proc()
1024 one->port.rs485.delay_rts_after_send; in max310x_rs_proc()
1025 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); in max310x_rs_proc()
1027 if (one->port.rs485.flags & SER_RS485_ENABLED) { in max310x_rs_proc()
1030 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_rs_proc()
1034 max310x_port_update(&one->port, MAX310X_MODE1_REG, in max310x_rs_proc()
1036 max310x_port_update(&one->port, MAX310X_MODE2_REG, in max310x_rs_proc()
1045 if ((rs485->delay_rts_before_send > 0x0f) || in max310x_rs485_config()
1046 (rs485->delay_rts_after_send > 0x0f)) in max310x_rs485_config()
1047 return -ERANGE; in max310x_rs485_config()
1049 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX | in max310x_rs485_config()
1051 memset(rs485->padding, 0, sizeof(rs485->padding)); in max310x_rs485_config()
1052 port->rs485 = *rs485; in max310x_rs485_config()
1054 schedule_work(&one->rs_work); in max310x_rs485_config()
1061 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_startup()
1064 s->devtype->power(port, 1); in max310x_startup()
1077 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | in max310x_startup()
1078 clamp(port->rs485.delay_rts_after_send, 0U, 15U); in max310x_startup()
1081 if (port->rs485.flags & SER_RS485_ENABLED) { in max310x_startup()
1086 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) in max310x_startup()
1109 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_shutdown()
1114 s->devtype->power(port, 0); in max310x_shutdown()
1119 struct max310x_port *s = dev_get_drvdata(port->dev); in max310x_type()
1121 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; in max310x_type()
1133 port->type = PORT_MAX310X; in max310x_config_port()
1138 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) in max310x_verify_port()
1139 return -EINVAL; in max310x_verify_port()
1140 if (s->irq != port->irq) in max310x_verify_port()
1141 return -EINVAL; in max310x_verify_port()
1174 for (i = 0; i < s->devtype->nr; i++) { in max310x_suspend()
1175 uart_suspend_port(&max310x_uart, &s->p[i].port); in max310x_suspend()
1176 s->devtype->power(&s->p[i].port, 0); in max310x_suspend()
1187 for (i = 0; i < s->devtype->nr; i++) { in max310x_resume()
1188 s->devtype->power(&s->p[i].port, 1); in max310x_resume()
1189 uart_resume_port(&max310x_uart, &s->p[i].port); in max310x_resume()
1202 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_get()
1212 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set()
1221 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_input()
1232 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_direction_output()
1246 struct uart_port *port = &s->p[offset / 4].port; in max310x_gpio_set_config()
1259 return -ENOTSUPP; in max310x_gpio_set_config()
1276 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); in max310x_probe()
1279 return -ENOMEM; in max310x_probe()
1285 s->clk = clk_osc; in max310x_probe()
1289 s->clk = clk_xtal; in max310x_probe()
1293 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || in max310x_probe()
1294 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { in max310x_probe()
1295 return -EPROBE_DEFER; in max310x_probe()
1298 return -EINVAL; in max310x_probe()
1301 ret = clk_prepare_enable(s->clk); in max310x_probe()
1305 freq = clk_get_rate(s->clk); in max310x_probe()
1308 ret = -ERANGE; in max310x_probe()
1312 s->regmap = regmap; in max310x_probe()
1313 s->devtype = devtype; in max310x_probe()
1317 ret = devtype->detect(dev); in max310x_probe()
1321 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1325 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, in max310x_probe()
1328 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); in max310x_probe()
1332 regmap_read(s->regmap, in max310x_probe()
1336 regmap_write(s->regmap, MAX310X_MODE1_REG + offs, in max310x_probe()
1337 devtype->mode1); in max310x_probe()
1341 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); in max310x_probe()
1343 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1348 ret = -ERANGE; in max310x_probe()
1353 s->p[i].port.line = line; in max310x_probe()
1354 s->p[i].port.dev = dev; in max310x_probe()
1355 s->p[i].port.irq = irq; in max310x_probe()
1356 s->p[i].port.type = PORT_MAX310X; in max310x_probe()
1357 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; in max310x_probe()
1358 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; in max310x_probe()
1359 s->p[i].port.iotype = UPIO_PORT; in max310x_probe()
1360 s->p[i].port.iobase = i * 0x20; in max310x_probe()
1361 s->p[i].port.membase = (void __iomem *)~0; in max310x_probe()
1362 s->p[i].port.uartclk = uartclk; in max310x_probe()
1363 s->p[i].port.rs485_config = max310x_rs485_config; in max310x_probe()
1364 s->p[i].port.ops = &max310x_ops; in max310x_probe()
1366 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); in max310x_probe()
1368 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); in max310x_probe()
1370 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); in max310x_probe()
1372 INIT_WORK(&s->p[i].md_work, max310x_md_proc); in max310x_probe()
1374 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); in max310x_probe()
1375 /* Initialize SPI-transfer buffers */ in max310x_probe()
1376 s->p[i].wr_header = (s->p[i].port.iobase + MAX310X_THR_REG) | in max310x_probe()
1378 s->p[i].rd_header = (s->p[i].port.iobase + MAX310X_RHR_REG); in max310x_probe()
1381 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1383 s->p[i].port.dev = NULL; in max310x_probe()
1389 devtype->power(&s->p[i].port, 0); in max310x_probe()
1394 s->gpio.owner = THIS_MODULE; in max310x_probe()
1395 s->gpio.parent = dev; in max310x_probe()
1396 s->gpio.label = devtype->name; in max310x_probe()
1397 s->gpio.direction_input = max310x_gpio_direction_input; in max310x_probe()
1398 s->gpio.get = max310x_gpio_get; in max310x_probe()
1399 s->gpio.direction_output= max310x_gpio_direction_output; in max310x_probe()
1400 s->gpio.set = max310x_gpio_set; in max310x_probe()
1401 s->gpio.set_config = max310x_gpio_set_config; in max310x_probe()
1402 s->gpio.base = -1; in max310x_probe()
1403 s->gpio.ngpio = devtype->nr * 4; in max310x_probe()
1404 s->gpio.can_sleep = 1; in max310x_probe()
1405 ret = devm_gpiochip_add_data(dev, &s->gpio, s); in max310x_probe()
1419 for (i = 0; i < devtype->nr; i++) { in max310x_probe()
1420 if (s->p[i].port.dev) { in max310x_probe()
1421 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_probe()
1422 clear_bit(s->p[i].port.line, max310x_lines); in max310x_probe()
1427 clk_disable_unprepare(s->clk); in max310x_probe()
1437 for (i = 0; i < s->devtype->nr; i++) { in max310x_remove()
1438 cancel_work_sync(&s->p[i].tx_work); in max310x_remove()
1439 cancel_work_sync(&s->p[i].md_work); in max310x_remove()
1440 cancel_work_sync(&s->p[i].rs_work); in max310x_remove()
1441 uart_remove_one_port(&max310x_uart, &s->p[i].port); in max310x_remove()
1442 clear_bit(s->p[i].port.line, max310x_lines); in max310x_remove()
1443 s->devtype->power(&s->p[i].port, 0); in max310x_remove()
1446 clk_disable_unprepare(s->clk); in max310x_remove()
1478 spi->bits_per_word = 8; in max310x_spi_probe()
1479 spi->mode = spi->mode ? : SPI_MODE_0; in max310x_spi_probe()
1480 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; in max310x_spi_probe()
1485 if (spi->dev.of_node) { in max310x_spi_probe()
1487 of_match_device(max310x_dt_ids, &spi->dev); in max310x_spi_probe()
1489 return -ENODEV; in max310x_spi_probe()
1491 devtype = (struct max310x_devtype *)of_id->data; in max310x_spi_probe()
1495 devtype = (struct max310x_devtype *)id_entry->driver_data; in max310x_spi_probe()
1498 regcfg.max_register = devtype->nr * 0x20 - 1; in max310x_spi_probe()
1501 return max310x_probe(&spi->dev, devtype, regmap, spi->irq); in max310x_spi_probe()
1506 return max310x_remove(&spi->dev); in max310x_spi_remove()