Lines Matching full:membase
164 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
186 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
189 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
203 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
205 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
212 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
214 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
216 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
218 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
227 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
232 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_break_ctl()
245 ch = readl(port->membase + UART_RBR(port)); in mvebu_uart_rx_chars()
259 ret = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
261 writel(ret, port->membase + UART_STAT); in mvebu_uart_rx_chars()
303 status = readl(port->membase + UART_STAT); in mvebu_uart_rx_chars()
316 writel(port->x_char, port->membase + UART_TSH(port)); in mvebu_uart_tx_chars()
328 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_tx_chars()
335 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_chars()
350 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_isr()
365 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_rx_isr()
377 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_tx_isr()
392 port->membase + UART_CTRL(port)); in mvebu_uart_startup()
396 ret = readl(port->membase + UART_STAT); in mvebu_uart_startup()
398 writel(ret, port->membase + UART_STAT); in mvebu_uart_startup()
400 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); in mvebu_uart_startup()
402 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_startup()
404 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_startup()
447 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_shutdown()
478 brdv = readl(port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
481 writel(brdv, port->membase + UART_BRDV); in mvebu_uart_baud_rate_set()
483 osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
485 writel(osamp, port->membase + UART_OSAMP); in mvebu_uart_baud_rate_set()
565 unsigned int st = readl(port->membase + UART_STAT); in mvebu_uart_get_poll_char()
570 return readl(port->membase + UART_RBR(port)); in mvebu_uart_get_poll_char()
578 st = readl(port->membase + UART_STAT); in mvebu_uart_put_poll_char()
586 writel(c, port->membase + UART_TSH(port)); in mvebu_uart_put_poll_char()
619 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
625 writel(c, port->membase + UART_STD_TSH); in mvebu_uart_putc()
628 st = readl(port->membase + UART_STAT); in mvebu_uart_putc()
647 if (!device->port.membase) in mvebu_uart_early_console_setup()
663 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmitr()
671 readl_poll_timeout_atomic(port->membase + UART_STAT, val, in wait_for_xmite()
678 writel(ch, port->membase + UART_TSH(port)); in mvebu_uart_console_putchar()
694 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; in mvebu_uart_console_write()
695 intr = readl(port->membase + UART_INTR(port)) & in mvebu_uart_console_write()
697 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
698 writel(0, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
705 writel(ier, port->membase + UART_CTRL(port)); in mvebu_uart_console_write()
708 ctl = intr | readl(port->membase + UART_INTR(port)); in mvebu_uart_console_write()
709 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_console_write()
729 if (!port->mapbase || !port->membase) { in mvebu_uart_console_setup()
781 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); in mvebu_uart_suspend()
782 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); in mvebu_uart_suspend()
783 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_suspend()
784 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); in mvebu_uart_suspend()
785 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); in mvebu_uart_suspend()
786 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); in mvebu_uart_suspend()
787 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); in mvebu_uart_suspend()
799 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); in mvebu_uart_resume()
800 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); in mvebu_uart_resume()
801 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); in mvebu_uart_resume()
802 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); in mvebu_uart_resume()
803 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); in mvebu_uart_resume()
804 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); in mvebu_uart_resume()
805 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); in mvebu_uart_resume()
873 port->membase = devm_ioremap_resource(&pdev->dev, reg); in mvebu_uart_probe()
874 if (IS_ERR(port->membase)) in mvebu_uart_probe()
875 return PTR_ERR(port->membase); in mvebu_uart_probe()
932 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); in mvebu_uart_probe()
934 writel(0, port->membase + UART_CTRL(port)); in mvebu_uart_probe()