Lines Matching +full:xps +full:- +full:uartlite +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
31 /* ---------------------------------------------------------------------
105 struct uartlite_data *pdata = port->private_data; in uart_in32()
107 return pdata->reg_ops->in(port->membase + offset); in uart_in32()
112 struct uartlite_data *pdata = port->private_data; in uart_out32()
114 pdata->reg_ops->out(val, port->membase + offset); in uart_out32()
119 /* ---------------------------------------------------------------------
125 struct tty_port *tport = &port->state->port; in ulite_receive()
135 port->icount.rx++; in ulite_receive()
139 port->icount.parity++; in ulite_receive()
143 port->icount.overrun++; in ulite_receive()
146 port->icount.frame++; in ulite_receive()
150 if (stat & port->ignore_status_mask & ULITE_STATUS_PARITY) in ulite_receive()
153 stat &= port->read_status_mask; in ulite_receive()
159 stat &= ~port->ignore_status_mask; in ulite_receive()
170 return 1; in ulite_receive()
175 struct circ_buf *xmit = &port->state->xmit; in ulite_transmit()
180 if (port->x_char) { in ulite_transmit()
181 uart_out32(port->x_char, ULITE_TX, port); in ulite_transmit()
182 port->x_char = 0; in ulite_transmit()
183 port->icount.tx++; in ulite_transmit()
184 return 1; in ulite_transmit()
190 uart_out32(xmit->buf[xmit->tail], ULITE_TX, port); in ulite_transmit()
191 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE-1); in ulite_transmit()
192 port->icount.tx++; in ulite_transmit()
198 return 1; in ulite_transmit()
208 spin_lock_irqsave(&port->lock, flags); in ulite_isr()
212 spin_unlock_irqrestore(&port->lock, flags); in ulite_isr()
217 if (n > 1) { in ulite_isr()
218 tty_flip_buffer_push(&port->state->port); in ulite_isr()
230 spin_lock_irqsave(&port->lock, flags); in ulite_tx_empty()
232 spin_unlock_irqrestore(&port->lock, flags); in ulite_tx_empty()
260 port->ignore_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_PARITY in ulite_stop_rx()
271 struct uartlite_data *pdata = port->private_data; in ulite_startup()
274 ret = clk_enable(pdata->clk); in ulite_startup()
276 dev_err(port->dev, "Failed to enable clock\n"); in ulite_startup()
280 ret = request_irq(port->irq, ulite_isr, IRQF_SHARED | IRQF_TRIGGER_RISING, in ulite_startup()
281 "uartlite", port); in ulite_startup()
294 struct uartlite_data *pdata = port->private_data; in ulite_shutdown()
298 free_irq(port->irq, port); in ulite_shutdown()
299 clk_disable(pdata->clk); in ulite_shutdown()
308 spin_lock_irqsave(&port->lock, flags); in ulite_set_termios()
310 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN in ulite_set_termios()
313 if (termios->c_iflag & INPCK) in ulite_set_termios()
314 port->read_status_mask |= in ulite_set_termios()
317 port->ignore_status_mask = 0; in ulite_set_termios()
318 if (termios->c_iflag & IGNPAR) in ulite_set_termios()
319 port->ignore_status_mask |= ULITE_STATUS_PARITY in ulite_set_termios()
323 if ((termios->c_cflag & CREAD) == 0) in ulite_set_termios()
324 port->ignore_status_mask |= in ulite_set_termios()
330 uart_update_timeout(port, termios->c_cflag, baud); in ulite_set_termios()
332 spin_unlock_irqrestore(&port->lock, flags); in ulite_set_termios()
337 return port->type == PORT_UARTLITE ? "uartlite" : NULL; in ulite_type()
342 release_mem_region(port->mapbase, ULITE_REGION); in ulite_release_port()
343 iounmap(port->membase); in ulite_release_port()
344 port->membase = NULL; in ulite_release_port()
349 struct uartlite_data *pdata = port->private_data; in ulite_request_port()
352 pr_debug("ulite console: port=%p; port->mapbase=%llx\n", in ulite_request_port()
353 port, (unsigned long long) port->mapbase); in ulite_request_port()
355 if (!request_mem_region(port->mapbase, ULITE_REGION, "uartlite")) { in ulite_request_port()
356 dev_err(port->dev, "Memory region busy\n"); in ulite_request_port()
357 return -EBUSY; in ulite_request_port()
360 port->membase = ioremap(port->mapbase, ULITE_REGION); in ulite_request_port()
361 if (!port->membase) { in ulite_request_port()
362 dev_err(port->dev, "Unable to map registers\n"); in ulite_request_port()
363 release_mem_region(port->mapbase, ULITE_REGION); in ulite_request_port()
364 return -EBUSY; in ulite_request_port()
367 pdata->reg_ops = &uartlite_be; in ulite_request_port()
373 pdata->reg_ops = &uartlite_le; in ulite_request_port()
381 port->type = PORT_UARTLITE; in ulite_config_port()
387 return -EINVAL; in ulite_verify_port()
393 struct uartlite_data *pdata = port->private_data; in ulite_pm()
396 clk_enable(pdata->clk); in ulite_pm()
398 clk_disable(pdata->clk); in ulite_pm()
443 /* ---------------------------------------------------------------------
455 * When using the Microblaze Debug Module this can take up to 1s in ulite_console_wait_tx()
458 while (1) { in ulite_console_wait_tx()
463 dev_warn(port->dev, in ulite_console_wait_tx()
483 int locked = 1; in ulite_console_write()
486 locked = spin_trylock_irqsave(&port->lock, flags); in ulite_console_write()
488 spin_lock_irqsave(&port->lock, flags); in ulite_console_write()
503 spin_unlock_irqrestore(&port->lock, flags); in ulite_console_write()
514 if (co->index >= 0 && co->index < ULITE_NR_UARTS) in ulite_console_setup()
515 port = ulite_ports + co->index; in ulite_console_setup()
518 if (!port || !port->mapbase) { in ulite_console_setup()
519 pr_debug("console on ttyUL%i not present\n", co->index); in ulite_console_setup()
520 return -ENODEV; in ulite_console_setup()
526 if (!port->membase) { in ulite_console_setup()
528 return -ENODEV; in ulite_console_setup()
545 .index = -1, /* Specified on the cmdline (e.g. console=ttyUL0 ) */
554 * set, or any other issue on the UARTLITE. in early_uartlite_putc()
560 /* read status bit - 0x8 offset */ in early_uartlite_putc()
561 while (--retries && (readl(port->membase + 8) & (1 << 3))) in early_uartlite_putc()
565 /* write to TX_FIFO - 0x4 offset */ in early_uartlite_putc()
567 writel(c & 0xff, port->membase + 4); in early_uartlite_putc()
573 struct earlycon_device *device = console->data; in early_uartlite_write()
574 uart_console_write(&device->port, s, n, early_uartlite_putc); in early_uartlite_write()
580 if (!device->port.membase) in early_uartlite_setup()
581 return -ENODEV; in early_uartlite_setup()
583 device->con->write = early_uartlite_write; in early_uartlite_setup()
586 EARLYCON_DECLARE(uartlite, early_uartlite_setup);
587 OF_EARLYCON_DECLARE(uartlite_b, "xlnx,opb-uartlite-1.00.b", early_uartlite_setup);
588 OF_EARLYCON_DECLARE(uartlite_a, "xlnx,xps-uartlite-1.00.a", early_uartlite_setup);
594 .driver_name = "uartlite",
604 /* ---------------------------------------------------------------------
608 /** ulite_assign: register a uartlite device with the driver
611 * @id: requested id number. Pass -1 for automatic port assignment
612 * @base: base address of uartlite registers
613 * @irq: irq number for uartlite
614 * @pdata: private data for uartlite
624 /* if id = -1; then scan for a free id and use that */ in ulite_assign()
632 return -EINVAL; in ulite_assign()
638 return -EBUSY; in ulite_assign()
643 spin_lock_init(&port->lock); in ulite_assign()
644 port->fifosize = 16; in ulite_assign()
645 port->regshift = 2; in ulite_assign()
646 port->iotype = UPIO_MEM; in ulite_assign()
647 port->iobase = 1; /* mark port in use */ in ulite_assign()
648 port->mapbase = base; in ulite_assign()
649 port->membase = NULL; in ulite_assign()
650 port->ops = &ulite_ops; in ulite_assign()
651 port->irq = irq; in ulite_assign()
652 port->flags = UPF_BOOT_AUTOCONF; in ulite_assign()
653 port->dev = dev; in ulite_assign()
654 port->type = PORT_UNKNOWN; in ulite_assign()
655 port->line = id; in ulite_assign()
656 port->private_data = pdata; in ulite_assign()
664 port->mapbase = 0; in ulite_assign()
672 /** ulite_release: register a uartlite device with the driver
684 port->mapbase = 0; in ulite_release()
691 * ulite_suspend - Stop the device.
707 * ulite_resume - Resume the device.
722 /* ---------------------------------------------------------------------
731 { .compatible = "xlnx,opb-uartlite-1.00.b", },
732 { .compatible = "xlnx,xps-uartlite-1.00.a", },
743 int id = pdev->id; in ulite_probe()
747 prop = of_get_property(pdev->dev.of_node, "port-number", NULL); in ulite_probe()
751 pdata = devm_kzalloc(&pdev->dev, sizeof(struct uartlite_data), in ulite_probe()
754 return -ENOMEM; in ulite_probe()
758 return -ENODEV; in ulite_probe()
762 return -ENXIO; in ulite_probe()
764 pdata->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); in ulite_probe()
765 if (IS_ERR(pdata->clk)) { in ulite_probe()
766 if (PTR_ERR(pdata->clk) != -ENOENT) in ulite_probe()
767 return PTR_ERR(pdata->clk); in ulite_probe()
773 pdata->clk = NULL; in ulite_probe()
776 ret = clk_prepare_enable(pdata->clk); in ulite_probe()
778 dev_err(&pdev->dev, "Failed to prepare clock\n"); in ulite_probe()
783 dev_dbg(&pdev->dev, "uartlite: calling uart_register_driver()\n"); in ulite_probe()
786 dev_err(&pdev->dev, "Failed to register driver\n"); in ulite_probe()
791 ret = ulite_assign(&pdev->dev, id, res->start, irq, pdata); in ulite_probe()
793 clk_disable(pdata->clk); in ulite_probe()
800 struct uart_port *port = dev_get_drvdata(&pdev->dev); in ulite_remove()
801 struct uartlite_data *pdata = port->private_data; in ulite_remove()
803 clk_disable_unprepare(pdata->clk); in ulite_remove()
804 return ulite_release(&pdev->dev); in ulite_remove()
808 MODULE_ALIAS("platform:uartlite");
814 .name = "uartlite",
820 /* ---------------------------------------------------------------------
827 pr_debug("uartlite: calling platform_driver_register()\n"); in ulite_init()
842 MODULE_DESCRIPTION("Xilinx uartlite serial driver");