Lines Matching +full:num +full:- +full:ss +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
17 * USBSS-DEV register interface.
22 * struct cdns3_usb_regs - device controller registers.
52 * @buf_addr: Address for On-chip Buffer operations.
53 * @buf_data: Data for On-chip Buffer operations.
54 * @buf_ctrl: On-chip Buffer Access Control.
122 /* USB_CONF - bitmasks */
131 /* Little Endian access - default */
145 /* DMA clock turn-off enable. */
147 /* DMA clock turn-off disable. */
172 /* U1 state entry enable (used in SS mode). */
174 /* U1 state entry disable (used in SS mode). */
176 /* U2 state entry enable (used in SS mode). */
178 /* U2 state entry disable (used in SS mode). */
180 /* U0 state entry request (used in SS mode). */
182 /* U1 state entry request (used in SS mode). */
184 /* U2 state entry request (used in SS mode). */
186 /* SS.Inactive state entry request (used in SS mode) */
189 /* USB_STS - bitmasks */
192 * 1 - device is in the configured state.
193 * 0 - device is not configured.
198 * On-chip memory overflow.
199 * 0 - On-chip memory status OK.
200 * 1 - On-chip memory overflow.
206 * 0 - USB in SuperSpeed mode disconnected.
207 * 1 - USB in SuperSpeed mode connected.
213 * 0 - single request.
214 * 1 - multiple TRB chain
221 * 0 - Undefined (value after reset).
222 * 1 - Low speed
223 * 2 - Full speed
224 * 3 - High speed
225 * 4 - Super speed
240 * 0 - Little Endian order (default after hardware reset).
241 * 1 - Big Endian order
246 * HS/FS clock turn-off status.
247 * 0 - hsfs clock is always on.
248 * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
254 * PCLK clock turn-off status.
255 * 0 - pclk clock is always on.
256 * 1 - pclk clock turn-off in U3 (SS mode) is enabled
263 * 0 - Internal reset is active.
264 * 1 - Internal reset is not active and controller is fully operational.
270 * 0 - disabled
271 * 1 - enabled
277 * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
278 * 1 - USB device is enabled (VBUS input is connected to the internal logic).
284 * 0 - USB device is default state.
285 * 1 - USB device is at least in address state.
291 * 0 - Entering to L1 LPM state disabled.
292 * 1 - Entering to L1 LPM state enabled.
297 * Internal VBUS connection status (used both in HS/FS and SS mode).
298 * 0 - internal VBUS is not detected.
299 * 1 - internal VBUS is detected.
305 * 0 - L0 State
306 * 1 - L1 State
307 * 2 - L2 State
308 * 3 - L3 State
317 * 0 - the disconnect bit for HS/FS mode is set .
318 * 1 - the disconnect bit for HS/FS mode is not set.
324 * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
325 * 1 - High Speed operations in USB2.0 (FS/HS).
330 * U1 state enable status (used in SS mode).
331 * 0 - Entering to U1 state disabled.
332 * 1 - Entering to U1 state enabled.
337 * U2 state enable status (used in SS mode).
338 * 0 - Entering to U2 state disabled.
339 * 1 - Entering to U2 state enabled.
344 * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
361 * DMA clock turn-off status.
362 * 0 - DMA clock is always on (default after hardware reset).
363 * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
369 * 0 - Little Endian order (default after hardware reset).
370 * 1 - Big Endian order.
375 /* USB_CMD - bitmasks */
387 /* Send Function Wake Device Notification TP (used only in SS mode). */
396 * in SS mode).
399 /* Send Custom Transaction Packet (used only in SS mode) */
401 /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
405 * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
406 * (used only in SS mode).
411 /* USB_ITPN - bitmasks */
413 * ITP(SS) / SOF (HS/FS) number
414 * In SS mode this field represent number of last ITP received from host.
420 /* USB_LPM - bitmasks */
427 /* USB_IEN - bitmasks */
428 /* SS connection interrupt enable */
430 /* SS disconnection interrupt enable. */
432 /* USB SS warm reset interrupt enable. */
434 /* USB SS hot reset interrupt enable */
436 /* SS link U3 state enter interrupt enable (suspend).*/
438 /* SS link U3 state exit interrupt enable (wakeup). */
440 /* SS link U2 state enter interrupt enable.*/
442 /* SS link U2 state exit interrupt enable.*/
444 /* SS link U1 state enter interrupt enable.*/
446 /* SS link U1 state exit interrupt enable.*/
470 /* Start of the USB SS warm reset interrupt enable.*/
472 /* End of the USB SS warm reset interrupt enable.*/
480 /* USB_ISTS - bitmasks */
481 /* SS Connection detected. */
483 /* SS Disconnection detected. */
528 /* USB_SEL - bitmasks */
532 /* Endpoint direction bit - 0 - OUT, 1 - IN. */
538 /* EP_TRADDR - bitmasks */
542 /* EP_CFG - bitmasks */
547 * 1 - isochronous
548 * 2 - bulk
549 * 3 - interrupt
553 /* Stream support enable (only in SS mode). */
555 /* TDL check (only in SS mode for BULK EP). */
557 /* SID check (only in SS mode for BULK OUT EP). */
561 /* Max burst size (used only in SS mode). */
577 /* EP_CMD - bitmasks */
594 * endpoints in SS mode).
599 * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
600 * Bits Removed from DEV_VER_V3 controller version.
607 /* ERDY Stream ID value (used in SS mode). */
611 /* EP_STS - bitmasks */
622 /* Stream Rejected (used only in SS mode) */
624 /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
628 /* Not ready (used only in SS mode). */
636 /* Prime (used only in SS mode. */
638 /* Stream error (used only in SS mode). */
644 /* Host Packet Pending (only for SS mode). */
663 /* EP_STS_SID - bitmasks */
664 /* Stream ID (used only in SS mode). */
668 /* EP_STS_EN - bitmasks */
694 /* DRBL- bitmasks */
699 /* EP_IEN - bitmasks */
704 /* EP_ISTS - bitmasks */
709 /* USB_PWR- bitmasks */
715 * Enables turning-off Reference Clock.
730 /* USB_CONF2- bitmasks */
744 /* USB_CAP1- bitmasks */
748 * 0x0 - OCP
749 * 0x1 - AHB,
750 * 0x2 - PLB
751 * 0x3 - AXI
752 * 0x4-0xF - reserved
762 * 0x0 - 8 bit interface,
763 * 0x1 - 16 bit interface,
764 * 0x2 - 32 bit interface
765 * 0x3 - 64 bit interface
766 * 0x4-0xF - reserved
776 * 0x0 - OCP
777 * 0x1 - AHB,
778 * 0x2 - PLB
779 * 0x3 - AXI
780 * 0x4-0xF - reserved
790 * 0x0 - reserved,
791 * 0x1 - reserved,
792 * 0x2 - 32 bit interface
793 * 0x3 - 64 bit interface
794 * 0x4-0xF - reserved
802 * 0x0 - USB PIPE,
803 * 0x1 - RMMI,
804 * 0x2-0xF - reserved
812 * 0x0 - 8 bit PIPE interface,
813 * 0x1 - 16 bit PIPE interface,
814 * 0x2 - 32 bit PIPE interface,
815 * 0x3 - 64 bit PIPE interface
816 * 0x4-0xF - reserved
833 * 0x0 - interface NOT implemented,
834 * 0x1 - interface implemented
840 * 0x0 - UTMI,
841 * 0x1 - ULPI
847 * 0x0 - 8 bit interface,
848 * 0x1 - 16 bit interface,
854 * 0x0 - pure device mode
855 * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
866 /* USB_CAP2- bitmasks */
868 * The actual size of the connected On-chip RAM memory in kB:
869 * - 0 means 256 kB (max supported mem size)
870 * - value other than 0 reflects the mem size in kB
875 * These field reflects width of on-chip RAM address bus width,
877 * 0x0-0x7 - reserved,
878 * 0x8 - support for 4kB mem,
879 * 0x9 - support for 8kB mem,
880 * 0xA - support for 16kB mem,
881 * 0xB - support for 32kB mem,
882 * 0xC - support for 64kB mem,
883 * 0xD - support for 128kB mem,
884 * 0xE - support for 256kB mem,
885 * 0xF - reserved
889 /* USB_CAP3- bitmasks */
892 /* USB_CAP4- bitmasks */
895 /* USB_CAP5- bitmasks */
898 /* USB_CAP6- bitmasks */
899 /* The USBSS-DEV Controller Internal build number. */
901 /* The USBSS-DEV Controller version number. */
909 /* DBG_LINK1- bitmasks */
922 * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
926 * 1: USBSS_DEV will not terminate Far-end receiver termination
957 /* DMA_AXI_CTRL- bitmasks */
968 /*-------------------------------------------------------------------------*/
970 * USBSS-DEV DMA interface.
989 *Only for ISOC endpoints - maximum number of TRBs is calculated as
990 * pow(2, bInterval-1) * number of usb requests. It is limitation made by
1000 * struct cdns3_trb - represent Transfer Descriptor block.
1030 /* Cycle bit - indicates TRB ownership by driver or hw*/
1046 * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
1047 * - Shall be set to 1 by Controller when Short Packet condition for this TRB
1073 /* Size of TD expressed in USB packets for SS mode. */
1077 /* transfer_len bitmasks - bits 31:24 */
1084 /*-------------------------------------------------------------------------*/
1102 /*-------------------------------------------------------------------------*/
1108 * struct cdns3_endpoint - extended device side representation of USB endpoint.
1113 * @trb_pool: transfer ring - array of transaction buffers
1118 * @descmis_req: internal transfer object used for getting data from on-chip
1122 * @num: endpoint number (1 - 15)
1168 u8 num; member
1199 * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
1216 * struct cdns3_request - extended device side representation of usb_request
1256 * struct cdns3_device - represent USB device.
1266 * @zlp_buf - zlp buffer
1274 * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
1283 * @onchip_buffers: number of available on-chip buffers.
1284 * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
1299 /* generic spin-lock for drivers */