1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
73 #define NAND_CMD_NONE		-1
82 #define NAND_DATA_IFACE_CHECK_ONLY	-1
96  * ecc.correct() returns -EBADMSG.
122  * Chip requires ready check on read (for auto-incremented sequential read).
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
172  * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173  * on the default ->cmdfunc() implementation, you may want to let the core
174  * handle the tCCS delay which is required when a column change (RNDIN or
176  * If your controller already takes care of this delay, you don't need to set
223  * struct nand_parameters - NAND generic parameters from the parameter page
245  * struct nand_id - NAND id structure
255  * struct nand_ecc_step_info - ECC step information of ECC engine
267  * struct nand_ecc_caps - capability of ECC engine
293  * struct nand_ecc_ctrl - Control structure for ECC
313  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
316  *		If -EBADMSG is returned the input buffers should be left
320  *			controller and always return contiguous in-band and
321  *			out-of-band data even if they're not stored
323  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
324  *			out-of-band data).
328  *			in-band and out-of-band data. ECC controller is
331  *			NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
332  *			out-of-band data).
335  *		any single ECC step, -EIO hw error
386  * struct nand_sdr_timings - SDR NAND chip timings
403  * @tAR_min: ALE to RE# delay
407  * @tCHZ_max: CE# high to output hi-Z
409  * @tCLR_min: CLE to RE# delay
416  * @tIR_min: Output hi-Z to RE# low
423  * @tRHZ_max: RE# high to output hi-Z
478  * struct nand_nvddr_timings - NV-DDR NAND chip timings
480  * This struct defines the timing requirements of a NV-DDR NAND data interface.
483  * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
484  * (chapter 4.18.2 NV-DDR)
495  * @tCAD_min: Command, Address, Data delay
509  * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
510  * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
564  * enum nand_interface_type - NAND interface type
574  * struct nand_interface_config - NAND interface timing
593  * nand_interface_is_sdr - get the interface type
598 	return conf->type == NAND_SDR_IFACE;  in nand_interface_is_sdr()
602  * nand_interface_is_nvddr - get the interface type
607 	return conf->type == NAND_NVDDR_IFACE;  in nand_interface_is_nvddr()
611  * nand_get_sdr_timings - get SDR timing from data interface
618 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
620 	return &conf->timings.sdr;  in nand_get_sdr_timings()
624  * nand_get_nvddr_timings - get NV-DDR timing from data interface
631 		return ERR_PTR(-EINVAL);  in nand_get_nvddr_timings()
633 	return &conf->timings.nvddr;  in nand_get_nvddr_timings()
637  * struct nand_op_cmd_instr - Definition of a command instruction
645  * struct nand_op_addr_instr - Definition of an address instruction
655  * struct nand_op_data_instr - Definition of a data instruction
660  * @force_8bit: force 8-bit access
676  * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
677  * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
684  * enum nand_op_instr_type - Definition of all instruction types
700  * struct nand_op_instr - Instruction object
702  * @ctx:  extra data associated to the instruction. You'll have to use the
709  * @delay_ns: delay the controller should apply after the instruction has been
815  * struct nand_subop - a sub operation
816  * @cs: the CS line to select for this NAND sub-operation
820  *			   of the sub-operation
822  *			of the sub-operation
828  * be split by the parser into sub-operations which will be passed to the
832 	unsigned int cs;  member
849  * struct nand_op_parser_addr_constraints - Constraints for address instructions
858  * struct nand_op_parser_data_constraints - Constraints for data instructions
866  * struct nand_op_parser_pattern_elem - One element of a pattern
916  * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
919  * @exec: the function that will issue a sub-operation
925  * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
948  * struct nand_op_parser - NAND controller operation parser descriptor
974  * struct nand_operation - NAND operation descriptor
975  * @cs: the CS line to select for this NAND operation
979  * The actual operation structure that will be passed to chip->exec_op().
982 	unsigned int cs;  member
989 		.cs = _cs,					\
1002 	switch (instr->type) {  in nand_op_trace()
1005 			 instr->ctx.cmd.opcode);  in nand_op_trace()
1009 			 instr->ctx.addr.naddrs,  in nand_op_trace()
1010 			 instr->ctx.addr.naddrs < 64 ?  in nand_op_trace()
1011 			 instr->ctx.addr.naddrs : 64,  in nand_op_trace()
1012 			 instr->ctx.addr.addrs);  in nand_op_trace()
1016 			 instr->ctx.data.len,  in nand_op_trace()
1017 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1018 			 ", force 8-bit" : "");  in nand_op_trace()
1022 			 instr->ctx.data.len,  in nand_op_trace()
1023 			 instr->ctx.data.force_8bit ?  in nand_op_trace()
1024 			 ", force 8-bit" : "");  in nand_op_trace()
1028 			 instr->ctx.waitrdy.timeout_ms);  in nand_op_trace()
1035  * struct nand_controller_ops - Controller operations
1045  *		 nand_controller_ops->attach_chip().
1048  *		 This method replaces chip->legacy.cmdfunc(),
1049  *		 chip->legacy.{read,write}_{buf,byte,word}(),
1050  *		 chip->legacy.dev_ready() and chip->legacy.waifunc().
1067  * struct nand_controller - Structure used to describe a NAND controller
1079 	mutex_init(&nfc->lock);  in nand_controller_init()
1083  * struct nand_legacy - NAND chip legacy fields/hooks
1102  * @chip_delay: chip dependent delay for transferring data from array to read
1113 	void (*select_chip)(struct nand_chip *chip, int cs);
1134  * struct nand_chip_ops - NAND chip operations
1139  * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1153  * struct nand_manufacturer - NAND manufacturer structure
1163  * struct nand_chip - NAND Private Flash Chip Data
1195  * @pagemask: Page number mask = number of (pages / chip) - 1
1201  * @pagecache.page: Page number currently in the cache. -1 means no page is
1208  * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1277 	return &chip->base.mtd;  in nand_to_mtd()
1282 	return chip->priv;  in nand_get_controller_data()
1287 	chip->priv = priv;  in nand_set_controller_data()
1293 	chip->manufacturer.priv = priv;  in nand_set_manufacturer_data()
1298 	return chip->manufacturer.priv;  in nand_get_manufacturer_data()
1313  * nand_get_interface_config - Retrieve the current interface configuration
1320 	return chip->current_interface_config;  in nand_get_interface_config()
1348 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1349 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1352  * struct nand_flash_dev - NAND Flash Device ID Structure
1353  * @name: a human-readable name of the NAND chip
1406 	WARN(nanddev_bits_per_cell(&chip->base) == 0,  in nand_is_slc()
1407 	     "chip->bits_per_cell is used uninitialized\n");  in nand_is_slc()
1408 	return nanddev_bits_per_cell(&chip->base) == 1;  in nand_is_slc()
1518 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1526  * nand_get_data_buf() - Get the internal page buffer
1529  * Returns the pre-allocated page buffer after invalidating the cache. This
1541 	chip->pagecache.page = -1;  in nand_get_data_buf()
1543 	return chip->data_buf;  in nand_get_data_buf()