Lines Matching +full:use +full:- +full:minimum +full:- +full:ecc
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
73 #define NAND_CMD_NONE -1
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
85 * Constants for Hardware ECC
87 /* Reset Hardware ECC for read */
89 /* Reset Hardware ECC for write */
91 /* Enable Hardware ECC before syndrome is read back from flash */
96 * ecc.correct() returns -EBADMSG.
122 * Chip requires ready check on read (for auto-incremented sequential read).
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
172 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173 * on the default ->cmdfunc() implementation, you may want to let the core
182 * Whether the NAND chip is a boot medium. Drivers might use this information
183 * to select ECC algorithms supported by the boot ROM or similar restrictions.
206 * Some controllers with pipelined ECC engines override the BBM marker with
207 * data or ECC bytes, thus making bad block detection through bad block marker
223 * struct nand_parameters - NAND generic parameters from the parameter page
245 * struct nand_id - NAND id structure
255 * struct nand_ecc_step_info - ECC step information of ECC engine
256 * @stepsize: data bytes per ECC step
267 * struct nand_ecc_caps - capability of ECC engine
268 * @stepinfos: array of ECC step information
269 * @nstepinfos: number of ECC step information
270 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
278 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
293 * struct nand_ecc_ctrl - Control structure for ECC
294 * @engine_type: ECC engine type
296 * @algo: ECC algorithm
297 * @steps: number of ECC steps per page
298 * @size: data bytes per ECC step
299 * @bytes: ECC bytes per step
300 * @strength: max number of correctible bits per ECC step
301 * @total: total number of ECC bytes per page
302 * @prepad: padding information for syndrome based ECC generators
303 * @postpad: padding information for syndrome based ECC generators
304 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
305 * @priv: pointer to private ECC control data
306 * @calc_buf: buffer for calculated ECC, size is oobsize.
307 * @code_buf: buffer for ECC read from flash, size is oobsize.
308 * @hwctl: function to control hardware ECC generator. Must only
309 * be provided if an hardware ECC is available
310 * @calculate: function for ECC calculation or readback from ECC hardware
311 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
313 * corrected bitflips, -EBADMSG if the number of bitflips exceed
314 * ECC strength, or any other error code if the error is not
316 * If -EBADMSG is returned the input buffers should be left
318 * @read_page_raw: function to read a raw page without ECC. This function
319 * should hide the specific layout used by the ECC
320 * controller and always return contiguous in-band and
321 * out-of-band data even if they're not stored
323 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
324 * out-of-band data).
325 * @write_page_raw: function to write a raw page without ECC. This function
326 * should hide the specific layout used by the ECC
328 * in-band and out-of-band data. ECC controller is
331 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
332 * out-of-band data).
333 * @read_page: function to read a page according to the ECC generator
335 * any single ECC step, -EIO hw error
336 * @read_subpage: function to read parts of the page covered by ECC;
338 * @write_subpage: function to write parts of the page covered by ECC.
339 * @write_page: function to write a page according to the ECC generator
341 * @write_oob_raw: function to write chip OOB data without ECC
342 * @read_oob_raw: function to read chip OOB data without ECC
386 * struct nand_sdr_timings - SDR NAND chip timings
407 * @tCHZ_max: CE# high to output hi-Z
416 * @tIR_min: Output hi-Z to RE# low
423 * @tRHZ_max: RE# high to output hi-Z
478 * struct nand_nvddr_timings - NV-DDR NAND chip timings
480 * This struct defines the timing requirements of a NV-DDR NAND data interface.
483 * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
484 * (chapter 4.18.2 NV-DDR)
509 * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
510 * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
564 * enum nand_interface_type - NAND interface type
574 * struct nand_interface_config - NAND interface timing
578 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
579 * @timings.nvddr: Use it when @type is %NAND_NVDDR_IFACE.
593 * nand_interface_is_sdr - get the interface type
598 return conf->type == NAND_SDR_IFACE; in nand_interface_is_sdr()
602 * nand_interface_is_nvddr - get the interface type
607 return conf->type == NAND_NVDDR_IFACE; in nand_interface_is_nvddr()
611 * nand_get_sdr_timings - get SDR timing from data interface
618 return ERR_PTR(-EINVAL); in nand_get_sdr_timings()
620 return &conf->timings.sdr; in nand_get_sdr_timings()
624 * nand_get_nvddr_timings - get NV-DDR timing from data interface
631 return ERR_PTR(-EINVAL); in nand_get_nvddr_timings()
633 return &conf->timings.nvddr; in nand_get_nvddr_timings()
637 * struct nand_op_cmd_instr - Definition of a command instruction
645 * struct nand_op_addr_instr - Definition of an address instruction
655 * struct nand_op_data_instr - Definition of a data instruction
660 * @force_8bit: force 8-bit access
676 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
684 * enum nand_op_instr_type - Definition of all instruction types
700 * struct nand_op_instr - Instruction object
702 * @ctx: extra data associated to the instruction. You'll have to use the
704 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
705 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
706 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
708 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
815 * struct nand_subop - a sub operation
816 * @cs: the CS line to select for this NAND sub-operation
820 * of the sub-operation
822 * of the sub-operation
828 * be split by the parser into sub-operations which will be passed to the
849 * struct nand_op_parser_addr_constraints - Constraints for address instructions
858 * struct nand_op_parser_data_constraints - Constraints for data instructions
866 * struct nand_op_parser_pattern_elem - One element of a pattern
916 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
919 * @exec: the function that will issue a sub-operation
925 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
948 * struct nand_op_parser - NAND controller operation parser descriptor
974 * struct nand_operation - NAND operation descriptor
979 * The actual operation structure that will be passed to chip->exec_op().
1002 switch (instr->type) { in nand_op_trace()
1005 instr->ctx.cmd.opcode); in nand_op_trace()
1009 instr->ctx.addr.naddrs, in nand_op_trace()
1010 instr->ctx.addr.naddrs < 64 ? in nand_op_trace()
1011 instr->ctx.addr.naddrs : 64, in nand_op_trace()
1012 instr->ctx.addr.addrs); in nand_op_trace()
1016 instr->ctx.data.len, in nand_op_trace()
1017 instr->ctx.data.force_8bit ? in nand_op_trace()
1018 ", force 8-bit" : ""); in nand_op_trace()
1022 instr->ctx.data.len, in nand_op_trace()
1023 instr->ctx.data.force_8bit ? in nand_op_trace()
1024 ", force 8-bit" : ""); in nand_op_trace()
1028 instr->ctx.waitrdy.timeout_ms); in nand_op_trace()
1035 * struct nand_controller_ops - Controller operations
1039 * size have been set up. ECC requirements are available if
1041 * choose the appropriate ECC configuration and allocate
1045 * nand_controller_ops->attach_chip().
1048 * This method replaces chip->legacy.cmdfunc(),
1049 * chip->legacy.{read,write}_{buf,byte,word}(),
1050 * chip->legacy.dev_ready() and chip->legacy.waifunc().
1067 * struct nand_controller - Structure used to describe a NAND controller
1079 mutex_init(&nfc->lock); in nand_controller_init()
1083 * struct nand_legacy - NAND chip legacy fields/hooks
1134 * struct nand_chip_ops - NAND chip operations
1139 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1153 * struct nand_manufacturer - NAND manufacturer structure
1163 * struct nand_chip - NAND Private Flash Chip Data
1170 * to use any of these fields/hooks, and if you're modifying an
1186 * @badblockbits: Minimum number of set bits in a good block's bad block marker
1195 * @pagemask: Page number mask = number of (pages / chip) - 1
1201 * @pagecache.page: Page number currently in the cache. -1 means no page is
1203 * @buf_align: Minimum buffer alignment required by a platform
1208 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1215 * @ecc: The ECC controller structure
1266 struct nand_ecc_ctrl ecc; member
1277 return &chip->base.mtd; in nand_to_mtd()
1282 return chip->priv; in nand_get_controller_data()
1287 chip->priv = priv; in nand_set_controller_data()
1293 chip->manufacturer.priv = priv; in nand_set_manufacturer_data()
1298 return chip->manufacturer.priv; in nand_get_manufacturer_data()
1313 * nand_get_interface_config - Retrieve the current interface configuration
1320 return chip->current_interface_config; in nand_get_interface_config()
1348 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1349 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1352 * struct nand_flash_dev - NAND Flash Device ID Structure
1353 * @name: a human-readable name of the NAND chip
1368 * @ecc: ECC correctability and step information from the datasheet.
1369 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1371 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1373 * For example, the "4bit ECC for each 512Byte" can be set with
1394 } ecc; member
1406 WARN(nanddev_bits_per_cell(&chip->base) == 0, in nand_is_slc()
1407 "chip->bits_per_cell is used uninitialized\n"); in nand_is_slc()
1408 return nanddev_bits_per_cell(&chip->base) == 1; in nand_is_slc()
1430 void *ecc, int ecclen,
1526 * nand_get_data_buf() - Get the internal page buffer
1529 * Returns the pre-allocated page buffer after invalidating the cache. This
1541 chip->pagecache.page = -1; in nand_get_data_buf()
1543 return chip->data_buf; in nand_get_data_buf()