Lines Matching +full:spe +full:- +full:pmu

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/include/asm/pmu.h
20  * The ARMv7 CPU PMU supports up to 32 event counters.
25  * ARM PMU hw_event flags
35 	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
38 [0 ... C(MAX) - 1] = {							\
39 	[0 ... C(OP_MAX) - 1] = {					\
40 		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
44 /* The events for a given PMU register set. */
47 	 * The events that are active on the PMU for the given index.
58 	 * Hardware lock to serialize accesses to PMU registers. Needed for the
81 	struct pmu	pmu;  member
85 	irqreturn_t	(*handle_irq)(struct arm_pmu *pmu);
102 	bool		secure_access; /* 32-bit ARM only */
111 	/* the attr_groups array must be NULL-terminated */
120 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
169 void armpmu_free(struct arm_pmu *pmu);
170 int armpmu_register(struct arm_pmu *pmu);
174 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
178 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1"