237 	struct clk				*gclk;  member
410 		clk_disable_unprepare(dev->gclk);  in mchp_spdifrx_hw_params()
413 	ret = clk_set_min_rate(dev->gclk, params_rate(params) *  in mchp_spdifrx_hw_params()
417 			"unable to set gclk min rate: rate %u * ratio %u + 1\n",  in mchp_spdifrx_hw_params()
421 	ret = clk_prepare_enable(dev->gclk);  in mchp_spdifrx_hw_params()
423 		dev_err(dev->dev, "unable to enable gclk: %d\n", ret);  in mchp_spdifrx_hw_params()
428 	dev_dbg(dev->dev, "GCLK range min set to %d\n",  in mchp_spdifrx_hw_params()
446 		clk_disable_unprepare(dev->gclk);  in mchp_spdifrx_hw_free()
650 	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled  in mchp_spdifrx_ulock_get()
680 	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled  in mchp_spdifrx_badf_get()
716 		ret = clk_prepare_enable(dev->gclk);  in mchp_spdifrx_signal_get()
734 		clk_disable_unprepare(dev->gclk);  in mchp_spdifrx_signal_get()
773 	 * The RSR.ULOCK has wrong value if both pclk and gclk are enabled  in mchp_spdifrx_rate_get()
790 	rate = clk_get_rate(dev->gclk);  in mchp_spdifrx_rate_get()
1002 	dev->gclk = devm_clk_get(&pdev->dev, "gclk");  in mchp_spdifrx_probe()
1003 	if (IS_ERR(dev->gclk)) {  in mchp_spdifrx_probe()
1004 		err = PTR_ERR(dev->gclk);  in mchp_spdifrx_probe()
1011 	 * Signal control need a valid rate on gclk. hw_params() configures  in mchp_spdifrx_probe()
1014 	 * gclk at a valid rate, here, in initialization, to simplify the  in mchp_spdifrx_probe()
1017 	clk_set_min_rate(dev->gclk, 48000 * SPDIFRX_GCLK_RATIO_MIN + 1);  in mchp_spdifrx_probe()