Lines Matching +full:sub +full:- +full:processor
1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
21 #include <sound/soc-dapm.h>
50 pll->id = id; in pll_init()
51 mutex_init(&pll->lock); in pll_init()
66 aif->id = id; in aif_init()
85 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; in init_coeff_ram_cache()
90 init_coeff_ram_cache(ram->cache); in coeff_ram_init()
91 mutex_init(&ram->lock); in coeff_ram_init()
103 status->streams |= mask; in set_aif_status_active()
111 status->streams &= mask; in set_aif_status_inactive()
116 return status->streams; in aifs_active()
121 return (0x03 << aif_id * 2) & status->streams; in aif_active()
282 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); in tscs454_data_init()
283 if (IS_ERR(tscs454->regmap)) { in tscs454_data_init()
284 ret = PTR_ERR(tscs454->regmap); in tscs454_data_init()
289 aif_init(&tscs454->aifs[i], i); in tscs454_data_init()
291 mutex_init(&tscs454->aifs_status_lock); in tscs454_data_init()
292 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
293 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
295 coeff_ram_init(&tscs454->dac_ram); in tscs454_data_init()
296 coeff_ram_init(&tscs454->spk_ram); in tscs454_data_init()
297 coeff_ram_init(&tscs454->sub_ram); in tscs454_data_init()
314 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_get()
315 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_get()
319 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_get()
320 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_get()
321 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_get()
322 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_get()
323 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_get()
324 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_get()
325 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_get()
326 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_get()
327 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_get()
329 return -EINVAL; in coeff_ram_get()
334 memcpy(ucontrol->value.bytes.data, in coeff_ram_get()
335 &coeff_ram[ctl->addr * COEFF_SIZE], params->max); in coeff_ram_get()
362 ret = -EIO; in write_coeff_ram()
363 dev_err(component->dev, in write_coeff_ram()
368 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); in write_coeff_ram()
370 dev_err(component->dev, in write_coeff_ram()
375 ret = regmap_bulk_write(tscs454->regmap, r_wr, in write_coeff_ram()
379 dev_err(component->dev, in write_coeff_ram()
395 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_put()
396 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_put()
397 unsigned int coeff_cnt = params->max / COEFF_SIZE; in coeff_ram_put()
407 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_put()
408 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_put()
409 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_put()
410 coeff_ram_synced = &tscs454->dac_ram.synced; in coeff_ram_put()
414 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_put()
415 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_put()
416 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_put()
417 coeff_ram_synced = &tscs454->spk_ram.synced; in coeff_ram_put()
421 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_put()
422 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_put()
423 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_put()
424 coeff_ram_synced = &tscs454->sub_ram.synced; in coeff_ram_put()
429 return -EINVAL; in coeff_ram_put()
436 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], in coeff_ram_put()
437 ucontrol->value.bytes.data, params->max); in coeff_ram_put()
439 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
440 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
446 ctl->addr, coeff_cnt); in coeff_ram_put()
448 dev_err(component->dev, in coeff_ram_put()
457 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
458 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
469 mutex_lock(&tscs454->dac_ram.lock); in coeff_ram_sync()
470 if (!tscs454->dac_ram.synced) { in coeff_ram_sync()
471 ret = write_coeff_ram(component, tscs454->dac_ram.cache, in coeff_ram_sync()
475 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
479 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
481 mutex_lock(&tscs454->spk_ram.lock); in coeff_ram_sync()
482 if (!tscs454->spk_ram.synced) { in coeff_ram_sync()
483 ret = write_coeff_ram(component, tscs454->spk_ram.cache, in coeff_ram_sync()
487 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
491 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
493 mutex_lock(&tscs454->sub_ram.lock); in coeff_ram_sync()
494 if (!tscs454->sub_ram.synced) { in coeff_ram_sync()
495 ret = write_coeff_ram(component, tscs454->sub_ram.cache, in coeff_ram_sync()
499 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
503 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
633 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in set_sysclk()
634 freq = clk_get_rate(tscs454->sysclk); in set_sysclk()
636 freq = tscs454->bclk_freq; in set_sysclk()
639 ret = -EINVAL; in set_sysclk()
640 dev_err(component->dev, in set_sysclk()
647 pll_ctl->settings[i].addr, in set_sysclk()
648 pll_ctl->settings[i].val); in set_sysclk()
650 dev_err(component->dev, in set_sysclk()
662 mutex_lock(&pll->lock); in reserve_pll()
663 pll->users++; in reserve_pll()
664 mutex_unlock(&pll->lock); in reserve_pll()
669 mutex_lock(&pll->lock); in free_pll()
670 pll->users--; in free_pll()
671 mutex_unlock(&pll->lock); in free_pll()
678 snd_soc_dapm_to_component(source->dapm); in pll_connected()
682 if (strstr(source->name, "PLL 1")) { in pll_connected()
683 mutex_lock(&tscs454->pll1.lock); in pll_connected()
684 users = tscs454->pll1.users; in pll_connected()
685 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
686 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, in pll_connected()
689 mutex_lock(&tscs454->pll2.lock); in pll_connected()
690 users = tscs454->pll2.users; in pll_connected()
691 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
692 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, in pll_connected()
707 snd_soc_dapm_to_component(w->dapm); in pll_power_event()
715 if (strstr(w->name, "PLL 1")) in pll_power_event()
734 dev_err(component->dev, "Failed to %s PLL %d (%d)\n", in pll_power_event()
745 dev_err(component->dev, in pll_power_event()
773 ret = -ENODEV; in aif_set_master()
774 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); in aif_set_master()
782 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", in aif_set_master()
795 ret = aif_set_master(component, aif->id, aif->master); in aif_prepare()
807 mutex_lock(&tscs454->aifs_status_lock); in aif_free()
809 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); in aif_free()
811 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); in aif_free()
813 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", in aif_free()
814 aif->id, tscs454->aifs_status.streams); in aif_free()
816 if (!aif_active(&tscs454->aifs_status, aif->id)) { in aif_free()
818 aif_set_master(component, aif->id, false); in aif_free()
819 dev_dbg(component->dev, "Freeing pll %d from aif %d\n", in aif_free()
820 aif->pll->id, aif->id); in aif_free()
821 free_pll(aif->pll); in aif_free()
824 if (!aifs_active(&tscs454->aifs_status)) { in aif_free()
825 dev_dbg(component->dev, "Freeing pll %d from ir\n", in aif_free()
826 tscs454->internal_rate.pll->id); in aif_free()
827 free_pll(tscs454->internal_rate.pll); in aif_free()
830 mutex_unlock(&tscs454->aifs_status_lock); in aif_free()
903 "DMic 2", "ClassD", "DAC", "Sub"};
953 SOC_DAPM_ENUM("Sub Mux", sub_mux_enum);
1025 SOC_DAPM_ENUM("Input Processor Channel 0 Enum",
1047 SOC_DAPM_ENUM("Input Processor Channel 1 Enum",
1101 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1107 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1113 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1131 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1132 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1135 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1138 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1187 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1191 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1195 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1201 "Pre Scale + EQ Band 0 - 1",
1202 "Pre Scale + EQ Band 0 - 2",
1203 "Pre Scale + EQ Band 0 - 3",
1204 "Pre Scale + EQ Band 0 - 4",
1205 "Pre Scale + EQ Band 0 - 5",
1251 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1254 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1479 (struct coeff_ram_ctl *)kcontrol->private_value; in bytes_info_ext()
1480 struct soc_bytes_ext *params = &ctl->bytes_ext; in bytes_info_ext()
1482 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in bytes_info_ext()
1483 ucontrol->count = params->max; in bytes_info_ext()
1583 SOC_ENUM("Input Processor Channel 0/1 Operation",
1596 SOC_ENUM("Input Processor Channel 2/3 Operation",
1707 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1712 SOC_SINGLE("Speaker De-Emphasis Switch",
1715 SOC_ENUM("Sub Polarity", sub_pol_enum),
1716 SOC_SINGLE("SUB Mute Switch", R_SUBCTL, FB_SUBCTL_SUBMUTE, 1, 0),
1717 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1719 SOC_SINGLE("Sub DC Removal Switch", R_DCCTL, FB_DCCTL_SUBDCBYP, 1, 1),
1742 SOC_SINGLE_TLV("Sub Volume", R_SUBVOL,
1767 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1784 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1801 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1826 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1896 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1913 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1930 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1955 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
2007 SOC_SINGLE("Sub EQ 2 Switch",
2009 SOC_ENUM("Sub EQ 2 Band", sub_eq_enums[0]),
2010 SOC_SINGLE("Sub EQ 1 Switch", R_SUBEQFILT, FB_SUBEQFILT_EQ1EN, 1, 0),
2011 SOC_ENUM("Sub EQ 1 Band", sub_eq_enums[1]),
2013 SOC_SINGLE("Sub MBC 3 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN3, 1, 0),
2014 SOC_SINGLE("Sub MBC 2 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN2, 1, 0),
2015 SOC_SINGLE("Sub MBC 1 Switch", R_SUBMBCEN, FB_SUBMBCEN_MBCEN1, 1, 0),
2017 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2018 SOC_ENUM("Sub MBC 3 Window", sub_mbc3_win_sel_enum),
2019 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2020 SOC_ENUM("Sub MBC 2 Window", sub_mbc2_win_sel_enum),
2021 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2022 SOC_ENUM("Sub MBC 1 Window", sub_mbc1_win_sel_enum),
2024 SOC_ENUM("Sub MBC 1 Phase Polarity", sub_mbc1_phase_pol_enum),
2025 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2029 SOC_SINGLE_TLV("Sub MBC 1 Compressor Threshold Volume", R_SUBMBCTHR1,
2033 SOC_ENUM("Sub MBC 1 Compressor Ratio", sub_mbc1_comp_rat_enum),
2036 SND_SOC_BYTES("Sub MBC 1 Attack", R_SUBMBCATK1L, 2),
2039 SND_SOC_BYTES("Sub MBC 1 Release", R_SUBMBCREL1L, 2),
2041 SOC_ENUM("Sub MBC 2 Phase Polarity", sub_mbc2_phase_pol_enum),
2042 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2046 SOC_SINGLE_TLV("Sub MBC 2 Compressor Threshold Volume", R_SUBMBCTHR2,
2050 SOC_ENUM("Sub MBC 2 Compressor Ratio", sub_mbc2_comp_rat_enum),
2053 SND_SOC_BYTES("Sub MBC 2 Attack", R_SUBMBCATK2L, 2),
2056 SND_SOC_BYTES("Sub MBC 2 Release", R_SUBMBCREL2L, 2),
2058 SOC_ENUM("Sub MBC 3 Phase Polarity", sub_mbc3_phase_pol_enum),
2059 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2063 SOC_SINGLE_TLV("Sub MBC 3 Threshold Volume", R_SUBMBCTHR3,
2067 SOC_ENUM("Sub MBC 3 Compressor Ratio", sub_mbc3_comp_rat_enum),
2070 SND_SOC_BYTES("Sub MBC 3 Attack", R_SUBMBCATK3L, 3),
2073 SND_SOC_BYTES("Sub MBC 3 Release", R_SUBMBCREL3L, 3),
2075 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2076 SOC_ENUM("Sub CLE Window", sub_cle_win_sel_enum),
2077 SOC_SINGLE("Sub CLE Expander Switch",
2079 SOC_SINGLE("Sub CLE Limiter Switch",
2081 SOC_SINGLE("Sub CLE Compressor Switch",
2084 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2088 SOC_SINGLE_TLV("Sub Compressor Threshold Volume", R_SUBCOMPTHR,
2092 SOC_ENUM("Sub Compressor Ratio", sub_comp_rat_enum),
2095 SND_SOC_BYTES("Sub Compressor Attack", R_SUBCOMPATKL, 2),
2098 SND_SOC_BYTES("Sub Compressor Release", R_SUBCOMPRELL, 2),
2100 SOC_SINGLE_TLV("Sub Limiter Threshold Volume", R_SUBLIMTHR,
2104 SOC_SINGLE_TLV("Sub Limiter Target Volume", R_SUBLIMTGT,
2109 SND_SOC_BYTES("Sub Limiter Attack", R_SUBLIMATKL, 2),
2112 SND_SOC_BYTES("Sub Limiter Release", R_SUBLIMRELL, 2),
2114 SOC_SINGLE_TLV("Sub Expander Threshold Volume", R_SUBEXPTHR,
2118 SOC_ENUM("Sub Expander Ratio", sub_exp_rat_enum),
2121 SND_SOC_BYTES("Sub Expander Attack", R_SUBEXPATKL, 2),
2124 SND_SOC_BYTES("Sub Expander Release", R_SUBEXPRELL, 2),
2126 SOC_SINGLE("Sub Treble Enhancement Switch",
2128 SOC_SINGLE("Sub Treble NLF Switch",
2130 SOC_SINGLE("Sub Bass Enhancement Switch",
2132 SOC_SINGLE("Sub Bass NLF Switch",
2276 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2277 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2278 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2279 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2280 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2281 COEFF_RAM_CTL("Sub Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2283 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2284 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2285 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2286 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2287 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2288 COEFF_RAM_CTL("Sub Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2290 COEFF_RAM_CTL("Sub Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2291 COEFF_RAM_CTL("Sub Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2293 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2294 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2295 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2296 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2297 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2298 COEFF_RAM_CTL("Sub Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2300 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2301 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2302 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2303 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2304 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2305 COEFF_RAM_CTL("Sub Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2307 COEFF_RAM_CTL("Sub Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2308 COEFF_RAM_CTL("Sub Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2310 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2311 COEFF_RAM_CTL("Sub Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2313 COEFF_RAM_CTL("Sub Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2314 COEFF_RAM_CTL("Sub Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2316 COEFF_RAM_CTL("Sub Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2318 COEFF_RAM_CTL("Sub Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2320 COEFF_RAM_CTL("Sub Bass Mix", COEFF_SIZE, 0x96),
2322 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2323 COEFF_RAM_CTL("Sub Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2325 COEFF_RAM_CTL("Sub Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2326 COEFF_RAM_CTL("Sub Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2328 COEFF_RAM_CTL("Sub Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2330 COEFF_RAM_CTL("Sub Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2332 COEFF_RAM_CTL("Sub Treb Mix", COEFF_SIZE, 0xad),
2334 COEFF_RAM_CTL("Sub 3D", COEFF_SIZE, 0xae),
2336 COEFF_RAM_CTL("Sub 3D Mix", COEFF_SIZE, 0xaf),
2338 COEFF_RAM_CTL("Sub MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2339 COEFF_RAM_CTL("Sub MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2341 COEFF_RAM_CTL("Sub MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2342 COEFF_RAM_CTL("Sub MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2344 COEFF_RAM_CTL("Sub MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2345 COEFF_RAM_CTL("Sub MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2364 SND_SOC_DAPM_ADC("Input Processor Channel 3", NULL,
2366 SND_SOC_DAPM_ADC("Input Processor Channel 2", NULL,
2368 SND_SOC_DAPM_ADC("Input Processor Channel 1", NULL,
2370 SND_SOC_DAPM_ADC("Input Processor Channel 0", NULL,
2377 SND_SOC_DAPM_SUPPLY("Sub Power", R_PWRM1, FB_PWRM1_SUBPU, 0, NULL, 0),
2409 SND_SOC_DAPM_DAC("Sub", NULL, R_PWRM4, FB_PWRM4_OPSUBPU, 0),
2425 SND_SOC_DAPM_MUX("Sub Mux", SND_SOC_NOPM, 0, 0,
2437 SND_SOC_DAPM_MUX("Input Processor Channel 0 Mux", SND_SOC_NOPM, 0, 0,
2444 SND_SOC_DAPM_MUX("Input Processor Channel 1 Mux", SND_SOC_NOPM, 0, 0,
2454 SND_SOC_DAPM_OUTPUT("Sub Out"),
2541 /* Sub Path */
2542 {"Sub Mux", "CH 4", "CH 4_5 Mux"},
2543 {"Sub Mux", "CH 5", "CH 4_5 Mux"},
2544 {"Sub Mux", "CH 4 + 5", "CH 4_5 Mux"},
2545 {"Sub Mux", "CH 2", "CH 2_3 Mux"},
2546 {"Sub Mux", "CH 3", "CH 2_3 Mux"},
2547 {"Sub Mux", "CH 2 + 3", "CH 2_3 Mux"},
2548 {"Sub Mux", "CH 0", "CH 0_1 Mux"},
2549 {"Sub Mux", "CH 1", "CH 0_1 Mux"},
2550 {"Sub Mux", "CH 0 + 1", "CH 0_1 Mux"},
2551 {"Sub Mux", "ADC/DMic 1 Left", "Input Processor Channel 0"},
2552 {"Sub Mux", "ADC/DMic 1 Right", "Input Processor Channel 1"},
2553 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 0"},
2554 {"Sub Mux", "ADC/DMic 1 Left Plus Right", "Input Processor Channel 1"},
2555 {"Sub Mux", "DMic 2 Left", "DMic 2"},
2556 {"Sub Mux", "DMic 2 Right", "DMic 2"},
2557 {"Sub Mux", "DMic 2 Left Plus Right", "DMic 2"},
2558 {"Sub Mux", "ClassD Left", "ClassD Left"},
2559 {"Sub Mux", "ClassD Right", "ClassD Right"},
2560 {"Sub Mux", "ClassD Left Plus Right", "ClassD Left"},
2561 {"Sub Mux", "ClassD Left Plus Right", "ClassD Right"},
2562 {"Sub", NULL, "Sub Mux"},
2563 {"Sub", NULL, "PLLs"},
2564 {"Sub Out", NULL, "Sub Power"},
2565 {"Sub Out", NULL, "Sub"},
2589 {"Input Processor Channel 0 Mux", "ADC", "ADC Channel 0 Mux"},
2590 {"Input Processor Channel 0 Mux", "DMic", "DMic 1"},
2592 {"Input Processor Channel 0", NULL, "PLLs"},
2593 {"Input Processor Channel 0", NULL, "Input Processor Channel 0 Mux"},
2595 {"Input Processor Channel 1 Mux", "ADC", "ADC Channel 1 Mux"},
2596 {"Input Processor Channel 1 Mux", "DMic", "DMic 1"},
2598 {"Input Processor Channel 1", NULL, "PLLs"},
2599 {"Input Processor Channel 1", NULL, "Input Processor Channel 1 Mux"},
2601 {"Input Processor Channel 2", NULL, "PLLs"},
2602 {"Input Processor Channel 2", NULL, "DMic 2"},
2604 {"Input Processor Channel 3", NULL, "PLLs"},
2605 {"Input Processor Channel 3", NULL, "DMic 2"},
2607 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2608 {"DAI 1 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2609 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 2"},
2610 {"DAI 1 Out Mux", "DMic 2", "Input Processor Channel 3"},
2612 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2613 {"DAI 2 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2614 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 2"},
2615 {"DAI 2 Out Mux", "DMic 2", "Input Processor Channel 3"},
2617 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 0"},
2618 {"DAI 3 Out Mux", "ADC/DMic 1", "Input Processor Channel 1"},
2619 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 2"},
2620 {"DAI 3 Out Mux", "DMic 2", "Input Processor Channel 3"},
2631 struct snd_soc_component *component = dai->component; in tscs454_set_sysclk()
2636 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); in tscs454_set_sysclk()
2641 if (bclk_dai != dai->id) in tscs454_set_sysclk()
2644 tscs454->bclk_freq = freq; in tscs454_set_sysclk()
2653 struct snd_soc_component *component = dai->component; in tscs454_set_bclk_ratio()
2657 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", in tscs454_set_bclk_ratio()
2658 dai->id, ratio); in tscs454_set_bclk_ratio()
2660 switch (dai->id) { in tscs454_set_bclk_ratio()
2674 ret = -EINVAL; in tscs454_set_bclk_ratio()
2675 dev_err(component->dev, "Unknown audio interface (%d)\n", ret); in tscs454_set_bclk_ratio()
2690 ret = -EINVAL; in tscs454_set_bclk_ratio()
2691 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); in tscs454_set_bclk_ratio()
2698 dev_err(component->dev, in tscs454_set_bclk_ratio()
2713 aif->master = true; in set_aif_master_from_fmt()
2716 aif->master = false; in set_aif_master_from_fmt()
2719 ret = -EINVAL; in set_aif_master_from_fmt()
2720 dev_err(component->dev, "Unsupported format (%d)\n", ret); in set_aif_master_from_fmt()
2744 ret = -EINVAL; in set_aif_tdm_delay()
2745 dev_err(component->dev, in set_aif_tdm_delay()
2752 dev_err(component->dev, "Failed to setup tdm format (%d)\n", in set_aif_tdm_delay()
2778 ret = -EINVAL; in set_aif_format_from_fmt()
2779 dev_err(component->dev, in set_aif_format_from_fmt()
2807 ret = -EINVAL; in set_aif_format_from_fmt()
2808 dev_err(component->dev, "Format unsupported (%d)\n", ret); in set_aif_format_from_fmt()
2815 dev_err(component->dev, "Failed to set DAI %d format (%d)\n", in set_aif_format_from_fmt()
2842 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2843 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2862 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2863 dev_err(component->dev, "Format unknown (%d)\n", ret); in set_aif_clock_format_from_fmt()
2870 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2881 struct snd_soc_component *component = dai->component; in tscs454_set_dai_fmt()
2883 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_set_dai_fmt()
2890 ret = set_aif_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2894 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2905 struct snd_soc_component *component = dai->component; in tscs454_dai1_set_tdm_slot()
2913 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2914 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2929 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2930 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2945 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2946 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2951 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2962 struct snd_soc_component *component = dai->component; in tscs454_dai23_set_tdm_slot()
2971 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2972 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
2976 switch (dai->id) { in tscs454_dai23_set_tdm_slot()
2984 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2985 dev_err(component->dev, "Unrecognized interface %d (%d)\n", in tscs454_dai23_set_tdm_slot()
2986 dai->id, ret); in tscs454_dai23_set_tdm_slot()
2998 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2999 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3014 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3015 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3020 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3078 ret = -EINVAL; in set_aif_fs()
3079 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); in set_aif_fs()
3094 ret = -EINVAL; in set_aif_fs()
3095 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); in set_aif_fs()
3102 dev_err(component->dev, in set_aif_fs()
3132 ret = -EINVAL; in set_aif_sample_format()
3133 dev_err(component->dev, "Unsupported format width (%d)\n", ret); in set_aif_sample_format()
3148 ret = -EINVAL; in set_aif_sample_format()
3149 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); in set_aif_sample_format()
3156 dev_err(component->dev, in set_aif_sample_format()
3168 struct snd_soc_component *component = dai->component; in tscs454_hw_params()
3171 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_params()
3175 mutex_lock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3177 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, in tscs454_hw_params()
3178 aif->id, fs); in tscs454_hw_params()
3180 if (!aif_active(&tscs454->aifs_status, aif->id)) { in tscs454_hw_params()
3182 aif->pll = &tscs454->pll1; in tscs454_hw_params()
3184 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3186 dev_dbg(component->dev, "Reserving pll %d for aif %d\n", in tscs454_hw_params()
3187 aif->pll->id, aif->id); in tscs454_hw_params()
3189 reserve_pll(aif->pll); in tscs454_hw_params()
3192 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ in tscs454_hw_params()
3195 tscs454->internal_rate.pll = &tscs454->pll1; in tscs454_hw_params()
3197 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
3199 dev_dbg(component->dev, "Reserving pll %d for ir\n", in tscs454_hw_params()
3200 tscs454->internal_rate.pll->id); in tscs454_hw_params()
3202 reserve_pll(tscs454->internal_rate.pll); in tscs454_hw_params()
3205 ret = set_aif_fs(component, aif->id, fs); in tscs454_hw_params()
3207 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); in tscs454_hw_params()
3211 ret = set_aif_sample_format(component, params_format(params), aif->id); in tscs454_hw_params()
3213 dev_err(component->dev, in tscs454_hw_params()
3218 set_aif_status_active(&tscs454->aifs_status, aif->id, in tscs454_hw_params()
3219 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_params()
3221 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", in tscs454_hw_params()
3222 aif->id, tscs454->aifs_status.streams); in tscs454_hw_params()
3226 mutex_unlock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3234 struct snd_soc_component *component = dai->component; in tscs454_hw_free()
3236 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_free()
3239 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_free()
3246 struct snd_soc_component *component = dai->component; in tscs454_prepare()
3248 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_prepare()
3283 switch (tscs454->sysclk_src_id) { in tscs454_probe()
3297 ret = -EINVAL; in tscs454_probe()
3298 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); in tscs454_probe()
3305 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); in tscs454_probe()
3309 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in tscs454_probe()
3334 .name = "tscs454-dai1",
3354 .name = "tscs454-dai2",
3374 .name = "tscs454-dai3",
3405 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); in tscs454_i2c_probe()
3407 return -ENOMEM; in tscs454_i2c_probe()
3416 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); in tscs454_i2c_probe()
3417 if (!IS_ERR(tscs454->sysclk)) { in tscs454_i2c_probe()
3419 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { in tscs454_i2c_probe()
3420 ret = PTR_ERR(tscs454->sysclk); in tscs454_i2c_probe()
3421 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); in tscs454_i2c_probe()
3425 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); in tscs454_i2c_probe()
3426 tscs454->sysclk_src_id = src; in tscs454_i2c_probe()
3428 ret = regmap_write(tscs454->regmap, in tscs454_i2c_probe()
3431 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); in tscs454_i2c_probe()
3434 regcache_mark_dirty(tscs454->regmap); in tscs454_i2c_probe()
3436 ret = regmap_register_patch(tscs454->regmap, tscs454_patch, in tscs454_i2c_probe()
3439 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); in tscs454_i2c_probe()
3443 regmap_write(tscs454->regmap, R_PAGESEL, 0x00); in tscs454_i2c_probe()
3445 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, in tscs454_i2c_probe()
3448 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); in tscs454_i2c_probe()