Lines Matching +full:designware +full:- +full:i2s
2 * ALSA SoC Synopsys I2S Audio Layer
45 i2s_write_reg(dev->i2s_base, TER(i), 0); in i2s_disable_channels()
48 i2s_write_reg(dev->i2s_base, RER(i), 0); in i2s_disable_channels()
58 i2s_read_reg(dev->i2s_base, TOR(i)); in i2s_clear_irqs()
61 i2s_read_reg(dev->i2s_base, ROR(i)); in i2s_clear_irqs()
72 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
73 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); in i2s_disable_irqs()
77 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
78 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); in i2s_disable_irqs()
90 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_enable_irqs()
91 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); in i2s_enable_irqs()
95 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_enable_irqs()
96 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); in i2s_enable_irqs()
109 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); in i2s_irq_handler()
119 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { in i2s_irq_handler()
128 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { in i2s_irq_handler()
135 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); in i2s_irq_handler()
141 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); in i2s_irq_handler()
155 struct i2s_clk_config_data *config = &dev->config; in i2s_start()
157 i2s_write_reg(dev->i2s_base, IER, 1); in i2s_start()
158 i2s_enable_irqs(dev, substream->stream, config->chan_nr); in i2s_start()
160 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in i2s_start()
161 i2s_write_reg(dev->i2s_base, ITER, 1); in i2s_start()
163 i2s_write_reg(dev->i2s_base, IRER, 1); in i2s_start()
165 i2s_write_reg(dev->i2s_base, CER, 1); in i2s_start()
172 i2s_clear_irqs(dev, substream->stream); in i2s_stop()
173 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in i2s_stop()
174 i2s_write_reg(dev->i2s_base, ITER, 0); in i2s_stop()
176 i2s_write_reg(dev->i2s_base, IRER, 0); in i2s_stop()
178 i2s_disable_irqs(dev, substream->stream, 8); in i2s_stop()
180 if (!dev->active) { in i2s_stop()
181 i2s_write_reg(dev->i2s_base, CER, 0); in i2s_stop()
182 i2s_write_reg(dev->i2s_base, IER, 0); in i2s_stop()
189 struct i2s_clk_config_data *config = &dev->config; in dw_i2s_config()
194 for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) { in dw_i2s_config()
196 i2s_write_reg(dev->i2s_base, TCR(ch_reg), in dw_i2s_config()
197 dev->xfer_resolution); in dw_i2s_config()
198 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), in dw_i2s_config()
199 dev->fifo_th - 1); in dw_i2s_config()
200 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); in dw_i2s_config()
202 i2s_write_reg(dev->i2s_base, RCR(ch_reg), in dw_i2s_config()
203 dev->xfer_resolution); in dw_i2s_config()
204 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), in dw_i2s_config()
205 dev->fifo_th - 1); in dw_i2s_config()
206 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1); in dw_i2s_config()
216 struct i2s_clk_config_data *config = &dev->config; in dw_i2s_hw_params()
221 config->data_width = 16; in dw_i2s_hw_params()
222 dev->ccr = 0x00; in dw_i2s_hw_params()
223 dev->xfer_resolution = 0x02; in dw_i2s_hw_params()
227 config->data_width = 24; in dw_i2s_hw_params()
228 dev->ccr = 0x08; in dw_i2s_hw_params()
229 dev->xfer_resolution = 0x04; in dw_i2s_hw_params()
233 config->data_width = 32; in dw_i2s_hw_params()
234 dev->ccr = 0x10; in dw_i2s_hw_params()
235 dev->xfer_resolution = 0x05; in dw_i2s_hw_params()
239 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); in dw_i2s_hw_params()
240 return -EINVAL; in dw_i2s_hw_params()
243 config->chan_nr = params_channels(params); in dw_i2s_hw_params()
245 switch (config->chan_nr) { in dw_i2s_hw_params()
252 dev_err(dev->dev, "channel not supported\n"); in dw_i2s_hw_params()
253 return -EINVAL; in dw_i2s_hw_params()
256 dw_i2s_config(dev, substream->stream); in dw_i2s_hw_params()
258 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
260 config->sample_rate = params_rate(params); in dw_i2s_hw_params()
262 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_hw_params()
263 if (dev->i2s_clk_cfg) { in dw_i2s_hw_params()
264 ret = dev->i2s_clk_cfg(config); in dw_i2s_hw_params()
266 dev_err(dev->dev, "runtime audio clk config fail\n"); in dw_i2s_hw_params()
270 u32 bitclk = config->sample_rate * in dw_i2s_hw_params()
271 config->data_width * 2; in dw_i2s_hw_params()
273 ret = clk_set_rate(dev->clk, bitclk); in dw_i2s_hw_params()
275 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", in dw_i2s_hw_params()
289 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in dw_i2s_prepare()
290 i2s_write_reg(dev->i2s_base, TXFFR, 1); in dw_i2s_prepare()
292 i2s_write_reg(dev->i2s_base, RXFFR, 1); in dw_i2s_prepare()
307 dev->active++; in dw_i2s_trigger()
314 dev->active--; in dw_i2s_trigger()
318 ret = -EINVAL; in dw_i2s_trigger()
331 if (dev->capability & DW_I2S_SLAVE) in dw_i2s_set_fmt()
334 ret = -EINVAL; in dw_i2s_set_fmt()
337 if (dev->capability & DW_I2S_MASTER) in dw_i2s_set_fmt()
340 ret = -EINVAL; in dw_i2s_set_fmt()
344 ret = -EINVAL; in dw_i2s_set_fmt()
347 dev_dbg(dev->dev, "dwc : Invalid master/slave format\n"); in dw_i2s_set_fmt()
348 ret = -EINVAL; in dw_i2s_set_fmt()
366 if (dw_dev->capability & DW_I2S_MASTER) in dw_i2s_runtime_suspend()
367 clk_disable(dw_dev->clk); in dw_i2s_runtime_suspend()
376 if (dw_dev->capability & DW_I2S_MASTER) { in dw_i2s_runtime_resume()
377 ret = clk_enable(dw_dev->clk); in dw_i2s_runtime_resume()
388 if (dev->capability & DW_I2S_MASTER) in dw_i2s_suspend()
389 clk_disable(dev->clk); in dw_i2s_suspend()
399 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_resume()
400 ret = clk_enable(dev->clk); in dw_i2s_resume()
420 .name = "dw-i2s",
427 * defined in the I2S block's configuration in terms of sound system
429 * according to the number of configuration bits describing an I2S
433 /* Maximum bit resolution of a channel - not uniformly spaced */
464 * the I2S block's configuration. in dw_configure_dai()
466 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); in dw_configure_dai()
467 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); in dw_configure_dai()
471 if (dev->capability & DWC_I2S_RECORD && in dw_configure_dai()
472 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) in dw_configure_dai()
475 if (dev->capability & DWC_I2S_PLAY && in dw_configure_dai()
476 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) in dw_configure_dai()
480 dev_dbg(dev->dev, " designware: play supported\n"); in dw_configure_dai()
483 return -EINVAL; in dw_configure_dai()
484 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) in dw_configure_dai()
486 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM; in dw_configure_dai()
487 dw_i2s_dai->playback.channels_max = in dw_configure_dai()
489 dw_i2s_dai->playback.formats = formats[idx]; in dw_configure_dai()
490 dw_i2s_dai->playback.rates = rates; in dw_configure_dai()
494 dev_dbg(dev->dev, "designware: record supported\n"); in dw_configure_dai()
497 return -EINVAL; in dw_configure_dai()
498 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) in dw_configure_dai()
500 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM; in dw_configure_dai()
501 dw_i2s_dai->capture.channels_max = in dw_configure_dai()
503 dw_i2s_dai->capture.formats = formats[idx]; in dw_configure_dai()
504 dw_i2s_dai->capture.rates = rates; in dw_configure_dai()
508 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); in dw_configure_dai()
509 dev->capability |= DW_I2S_MASTER; in dw_configure_dai()
511 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); in dw_configure_dai()
512 dev->capability |= DW_I2S_SLAVE; in dw_configure_dai()
515 dev->fifo_th = fifo_depth / 2; in dw_configure_dai()
524 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); in dw_configure_dai_by_pd()
529 return -EINVAL; in dw_configure_dai_by_pd()
531 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); in dw_configure_dai_by_pd()
535 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) in dw_configure_dai_by_pd()
538 dev->play_dma_data.pd.data = pdata->play_dma_data; in dw_configure_dai_by_pd()
539 dev->capture_dma_data.pd.data = pdata->capture_dma_data; in dw_configure_dai_by_pd()
540 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_pd()
541 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_pd()
542 dev->play_dma_data.pd.max_burst = 16; in dw_configure_dai_by_pd()
543 dev->capture_dma_data.pd.max_burst = 16; in dw_configure_dai_by_pd()
544 dev->play_dma_data.pd.addr_width = bus_widths[idx]; in dw_configure_dai_by_pd()
545 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; in dw_configure_dai_by_pd()
546 dev->play_dma_data.pd.filter = pdata->filter; in dw_configure_dai_by_pd()
547 dev->capture_dma_data.pd.filter = pdata->filter; in dw_configure_dai_by_pd()
556 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); in dw_configure_dai_by_dt()
557 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); in dw_configure_dai_by_dt()
564 return -EINVAL; in dw_configure_dai_by_dt()
573 dev->capability |= DWC_I2S_PLAY; in dw_configure_dai_by_dt()
574 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_dt()
575 dev->play_dma_data.dt.addr_width = bus_widths[idx]; in dw_configure_dai_by_dt()
576 dev->play_dma_data.dt.fifo_size = fifo_depth * in dw_configure_dai_by_dt()
578 dev->play_dma_data.dt.maxburst = 16; in dw_configure_dai_by_dt()
583 dev->capability |= DWC_I2S_RECORD; in dw_configure_dai_by_dt()
584 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_dt()
585 dev->capture_dma_data.dt.addr_width = bus_widths[idx]; in dw_configure_dai_by_dt()
586 dev->capture_dma_data.dt.fifo_size = fifo_depth * in dw_configure_dai_by_dt()
588 dev->capture_dma_data.dt.maxburst = 16; in dw_configure_dai_by_dt()
599 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data); in dw_i2s_dai_probe()
605 const struct i2s_platform_data *pdata = pdev->dev.platform_data; in dw_i2s_probe()
612 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); in dw_i2s_probe()
614 return -ENOMEM; in dw_i2s_probe()
616 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); in dw_i2s_probe()
618 return -ENOMEM; in dw_i2s_probe()
620 dw_i2s_dai->ops = &dw_i2s_dai_ops; in dw_i2s_probe()
621 dw_i2s_dai->probe = dw_i2s_dai_probe; in dw_i2s_probe()
624 dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); in dw_i2s_probe()
625 if (IS_ERR(dev->i2s_base)) in dw_i2s_probe()
626 return PTR_ERR(dev->i2s_base); in dw_i2s_probe()
628 dev->dev = &pdev->dev; in dw_i2s_probe()
632 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, in dw_i2s_probe()
633 pdev->name, dev); in dw_i2s_probe()
635 dev_err(&pdev->dev, "failed to request irq\n"); in dw_i2s_probe()
640 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; in dw_i2s_probe()
641 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; in dw_i2s_probe()
643 dev->capability = pdata->cap; in dw_i2s_probe()
645 dev->quirks = pdata->quirks; in dw_i2s_probe()
646 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { in dw_i2s_probe()
647 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; in dw_i2s_probe()
648 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; in dw_i2s_probe()
658 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_probe()
660 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; in dw_i2s_probe()
661 if (!dev->i2s_clk_cfg) { in dw_i2s_probe()
662 dev_err(&pdev->dev, "no clock configure method\n"); in dw_i2s_probe()
663 return -ENODEV; in dw_i2s_probe()
666 dev->clk = devm_clk_get(&pdev->dev, clk_id); in dw_i2s_probe()
668 if (IS_ERR(dev->clk)) in dw_i2s_probe()
669 return PTR_ERR(dev->clk); in dw_i2s_probe()
671 ret = clk_prepare_enable(dev->clk); in dw_i2s_probe()
676 dev_set_drvdata(&pdev->dev, dev); in dw_i2s_probe()
677 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, in dw_i2s_probe()
680 dev_err(&pdev->dev, "not able to register dai\n"); in dw_i2s_probe()
687 dev->use_pio = true; in dw_i2s_probe()
689 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, in dw_i2s_probe()
691 dev->use_pio = false; in dw_i2s_probe()
695 dev_err(&pdev->dev, "could not register pcm: %d\n", in dw_i2s_probe()
701 pm_runtime_enable(&pdev->dev); in dw_i2s_probe()
705 if (dev->capability & DW_I2S_MASTER) in dw_i2s_probe()
706 clk_disable_unprepare(dev->clk); in dw_i2s_probe()
712 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); in dw_i2s_remove()
714 if (dev->capability & DW_I2S_MASTER) in dw_i2s_remove()
715 clk_disable_unprepare(dev->clk); in dw_i2s_remove()
717 pm_runtime_disable(&pdev->dev); in dw_i2s_remove()
723 { .compatible = "snps,designware-i2s", },
738 .name = "designware-i2s",
747 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");