Lines Matching +full:1 +full:c0
37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
76 1: add r4, r4, #1 @ area size *= 2
77 movs r3, r3, lsr #1
78 bne 1b @ count not zero r-shift
79 orr r0, r0, r4, lsl #1 @ the area register value
80 orr r0, r0, #1 @ set enable bit
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
89 1: add r4, r4, #1 @ area size *= 2
90 movs r3, r3, lsr #1
91 bne 1b @ count not zero r-shift
92 orr r0, r0, r4, lsl #1 @ the area register value
93 orr r0, r0, #1 @ set enable bit
97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
101 mov r0, #0x02 @ Region 1 write bufferred
103 mcr p15, 0, r0, c3, c0
106 sub r0, r0, #1 @ r0 = 0xffff
107 mcr p15, 0, r0, c5, c0 @ all read/write access
109 mrc p15, 0, r0, c1, c0 @ get control register
121 define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1