1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 1995-2001 Russell King
105  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
112 	u32 i, affinity, fs[4], bits[4], ls;  in smp_build_mpidr_hash()  local
115 	 * Pre-scan the list of MPIDRS and filter out bits that do  in smp_build_mpidr_hash()
120 	pr_debug("mask of set bits %#llx\n", mask);  in smp_build_mpidr_hash()
123 	 * check how many bits are required to represent them.  in smp_build_mpidr_hash()
128 		 * Find the MSB bit and LSB bits position  in smp_build_mpidr_hash()
129 		 * to determine how many bits are required  in smp_build_mpidr_hash()
132 		ls = fls(affinity);  in smp_build_mpidr_hash()
133 		fs[i] = affinity ? ffs(affinity) - 1 : 0;  in smp_build_mpidr_hash()
134 		bits[i] = ls - fs[i];  in smp_build_mpidr_hash()
138 	 * significant bits at each affinity level and by shifting  in smp_build_mpidr_hash()
139 	 * them in order to compress the 32 bits values space to a  in smp_build_mpidr_hash()
147 	mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];  in smp_build_mpidr_hash()
148 	mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -  in smp_build_mpidr_hash()
149 						(bits[1] + bits[0]);  in smp_build_mpidr_hash()
151 				  fs[3] - (bits[2] + bits[1] + bits[0]);  in smp_build_mpidr_hash()
153 	mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];  in smp_build_mpidr_hash()
154 	pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",  in smp_build_mpidr_hash()
160 		mpidr_hash.bits);  in smp_build_mpidr_hash()
200 			"The dtb must be 8-byte aligned and must not exceed 2 MB in size\n"  in setup_machine_fdt()
207 		 * or else we could end-up printing non-initialized data, etc.  in setup_machine_fdt()
213 	/* Early fixups are done, map the FDT as read-only now */  in setup_machine_fdt()
232 	kernel_code.end     = __pa_symbol(__init_begin - 1);  in request_standard_resources()
234 	kernel_data.end     = __pa_symbol(_end - 1);  in request_standard_resources()
247 			res->name  = "reserved";  in request_standard_resources()
248 			res->flags = IORESOURCE_MEM;  in request_standard_resources()
249 			res->start = __pfn_to_phys(memblock_region_reserved_base_pfn(region));  in request_standard_resources()
250 			res->end = __pfn_to_phys(memblock_region_reserved_end_pfn(region)) - 1;  in request_standard_resources()
252 			res->name  = "System RAM";  in request_standard_resources()
253 			res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;  in request_standard_resources()
254 			res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));  in request_standard_resources()
255 			res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;  in request_standard_resources()
270 		if (!memblock_is_region_reserved(mem->start, mem_size))  in reserve_memblock_reserved_regions()
276 			start = max(PFN_PHYS(PFN_DOWN(r_start)), mem->start);  in reserve_memblock_reserved_regions()
277 			end = min(PFN_PHYS(PFN_UP(r_end)) - 1, mem->end);  in reserve_memblock_reserved_regions()
279 			if (start > mem->end || end < mem->start)  in reserve_memblock_reserved_regions()
290 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
306 	 * If know now we are going to need KPTI then use non-global  in setup_arch()
355 	/* Parse the ACPI tables for possible boot-time configuration */  in setup_arch()
388 		pr_err("WARNING: x1-x3 nonzero in violation of boot protocol:\n"  in setup_arch()
400 	if (ops && ops->cpu_can_disable)  in cpu_can_disable()
401 		return ops->cpu_can_disable(cpu);  in cpu_can_disable()
412 		cpu->hotpluggable = cpu_can_disable(i);  in topology_init()
457 		panic("Non-EFI boot detected with MMU and caches enabled");  in check_mmu_enabled_at_boot()