Lines Matching +full:enum +full:- +full:name
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
36 enum reg0i15_op {
40 enum reg0i26_op {
45 enum reg1i20_op {
54 enum reg1i21_op {
61 enum reg2_op {
70 enum reg2i5_op {
76 enum reg2i6_op {
82 enum reg2i12_op {
106 enum reg2i14_op {
117 enum reg2i16_op {
127 enum reg2bstrd_op {
132 enum reg3_op {
242 enum reg3sa2_op {
355 enum loongarch_gpr {
394 return val & (1UL << (bit - 1)); in is_imm_negative()
399 return ip->reg0i15_format.opcode == break_op; in is_break_ins()
404 return ip->reg1i20_format.opcode >= pcaddi_op && in is_pc_ins()
405 ip->reg1i20_format.opcode <= pcaddu18i_op; in is_pc_ins()
410 return ip->reg1i21_format.opcode >= beqz_op && in is_branch_ins()
411 ip->reg1i21_format.opcode <= bgeu_op; in is_branch_ins()
417 return ip->reg2i12_format.opcode == std_op && in is_ra_save_ins()
418 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && in is_ra_save_ins()
419 ip->reg2i12_format.rd == LOONGARCH_GPR_RA && in is_ra_save_ins()
420 !is_imm12_negative(ip->reg2i12_format.immediate); in is_ra_save_ins()
425 /* addi.d $sp, $sp, -imm */ in is_stack_alloc_ins()
426 return ip->reg2i12_format.opcode == addid_op && in is_stack_alloc_ins()
427 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && in is_stack_alloc_ins()
428 ip->reg2i12_format.rd == LOONGARCH_GPR_SP && in is_stack_alloc_ins()
429 is_imm12_negative(ip->reg2i12_format.immediate); in is_stack_alloc_ins()
434 switch (ip->reg0i26_format.opcode) { in is_self_loop_ins()
437 if (ip->reg0i26_format.immediate_l == 0 in is_self_loop_ins()
438 && ip->reg0i26_format.immediate_h == 0) in is_self_loop_ins()
442 switch (ip->reg1i21_format.opcode) { in is_self_loop_ins()
446 if (ip->reg1i21_format.immediate_l == 0 in is_self_loop_ins()
447 && ip->reg1i21_format.immediate_h == 0) in is_self_loop_ins()
451 switch (ip->reg2i16_format.opcode) { in is_self_loop_ins()
458 if (ip->reg2i16_format.immediate == 0) in is_self_loop_ins()
462 if (regs->regs[ip->reg2i16_format.rj] + in is_self_loop_ins()
463 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip) in is_self_loop_ins()
487 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
488 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
490 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
491 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
492 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
493 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
497 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1)); in signed_imm_check()
505 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \ argument
506 static inline void emit_##NAME(union loongarch_instruction *insn, \
509 insn->reg0i15_format.opcode = OP; \
510 insn->reg0i15_format.immediate = imm; \
515 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \ in DEF_EMIT_REG0I15_FORMAT() argument
516 static inline void emit_##NAME(union loongarch_instruction *insn, \ in DEF_EMIT_REG0I15_FORMAT()
525 insn->reg0i26_format.opcode = OP; \ in DEF_EMIT_REG0I15_FORMAT()
526 insn->reg0i26_format.immediate_l = immediate_l; \ in DEF_EMIT_REG0I15_FORMAT()
527 insn->reg0i26_format.immediate_h = immediate_h; \ in DEF_EMIT_REG0I15_FORMAT()
533 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \ argument
534 static inline void emit_##NAME(union loongarch_instruction *insn, \
535 enum loongarch_gpr rd, int imm) \
537 insn->reg1i20_format.opcode = OP; \
538 insn->reg1i20_format.immediate = imm; \
539 insn->reg1i20_format.rd = rd; \
546 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \ argument
547 static inline void emit_##NAME(union loongarch_instruction *insn, \
548 enum loongarch_gpr rd, \
549 enum loongarch_gpr rj) \
551 insn->reg2_format.opcode = OP; \
552 insn->reg2_format.rd = rd; \
553 insn->reg2_format.rj = rj; \
560 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \ argument
561 static inline void emit_##NAME(union loongarch_instruction *insn, \
562 enum loongarch_gpr rd, \
563 enum loongarch_gpr rj, \
566 insn->reg2i5_format.opcode = OP; \
567 insn->reg2i5_format.immediate = imm; \
568 insn->reg2i5_format.rd = rd; \
569 insn->reg2i5_format.rj = rj; \
576 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \ argument
577 static inline void emit_##NAME(union loongarch_instruction *insn, \
578 enum loongarch_gpr rd, \
579 enum loongarch_gpr rj, \
582 insn->reg2i6_format.opcode = OP; \
583 insn->reg2i6_format.immediate = imm; \
584 insn->reg2i6_format.rd = rd; \
585 insn->reg2i6_format.rj = rj; \
592 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \ argument
593 static inline void emit_##NAME(union loongarch_instruction *insn, \
594 enum loongarch_gpr rd, \
595 enum loongarch_gpr rj, \
598 insn->reg2i12_format.opcode = OP; \
599 insn->reg2i12_format.immediate = imm; \
600 insn->reg2i12_format.rd = rd; \
601 insn->reg2i12_format.rj = rj; \
619 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \ argument
620 static inline void emit_##NAME(union loongarch_instruction *insn, \
621 enum loongarch_gpr rd, \
622 enum loongarch_gpr rj, \
625 insn->reg2i14_format.opcode = OP; \
626 insn->reg2i14_format.immediate = imm; \
627 insn->reg2i14_format.rd = rd; \
628 insn->reg2i14_format.rj = rj; \
640 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \ argument
641 static inline void emit_##NAME(union loongarch_instruction *insn, \
642 enum loongarch_gpr rj, \
643 enum loongarch_gpr rd, \
646 insn->reg2i16_format.opcode = OP; \
647 insn->reg2i16_format.immediate = offset; \
648 insn->reg2i16_format.rj = rj; \
649 insn->reg2i16_format.rd = rd; \
660 enum loongarch_gpr rd,
661 enum loongarch_gpr rj,
664 insn->reg2i16_format.opcode = jirl_op;
665 insn->reg2i16_format.immediate = offset;
666 insn->reg2i16_format.rd = rd;
667 insn->reg2i16_format.rj = rj;
670 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \ argument
671 static inline void emit_##NAME(union loongarch_instruction *insn, \
672 enum loongarch_gpr rd, \
673 enum loongarch_gpr rj, \
677 insn->reg2bstrd_format.opcode = OP; \
678 insn->reg2bstrd_format.msbd = msbd; \
679 insn->reg2bstrd_format.lsbd = lsbd; \
680 insn->reg2bstrd_format.rj = rj; \
681 insn->reg2bstrd_format.rd = rd; \
686 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \ argument
687 static inline void emit_##NAME(union loongarch_instruction *insn, \
688 enum loongarch_gpr rd, \
689 enum loongarch_gpr rj, \
690 enum loongarch_gpr rk) \
692 insn->reg3_format.opcode = OP; \
693 insn->reg3_format.rd = rd; \
694 insn->reg3_format.rj = rj; \
695 insn->reg3_format.rk = rk; \
731 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \ argument
732 static inline void emit_##NAME(union loongarch_instruction *insn, \
733 enum loongarch_gpr rd, \
734 enum loongarch_gpr rj, \
735 enum loongarch_gpr rk, \
738 insn->reg3sa2_format.opcode = OP; \
739 insn->reg3sa2_format.immediate = imm; \
740 insn->reg3sa2_format.rd = rd; \
741 insn->reg3sa2_format.rj = rj; \
742 insn->reg3sa2_format.rk = rk; \