Lines Matching +full:clock +full:- +full:mult
1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \
48 #define CPG_PLLxCR0_NI GENMASK(27, 20) /* Integer mult. factor */
74 unsigned int mult; in cpg_pll_clk_recalc_rate() local
76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; in cpg_pll_clk_recalc_rate()
78 return parent_rate * mult * 2; in cpg_pll_clk_recalc_rate()
84 unsigned int min_mult, max_mult, mult; in cpg_pll_clk_determine_rate() local
87 prate = req->best_parent_rate * 2; in cpg_pll_clk_determine_rate()
88 min_mult = max(div64_ul(req->min_rate, prate), 1ULL); in cpg_pll_clk_determine_rate()
89 max_mult = min(div64_ul(req->max_rate, prate), 256ULL); in cpg_pll_clk_determine_rate()
91 return -EINVAL; in cpg_pll_clk_determine_rate()
93 mult = DIV_ROUND_CLOSEST_ULL(req->rate, prate); in cpg_pll_clk_determine_rate()
94 mult = clamp(mult, min_mult, max_mult); in cpg_pll_clk_determine_rate()
96 req->rate = prate * mult; in cpg_pll_clk_determine_rate()
104 unsigned int mult; in cpg_pll_clk_set_rate() local
107 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * 2); in cpg_pll_clk_set_rate()
108 mult = clamp(mult, 1U, 256U); in cpg_pll_clk_set_rate()
110 if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) in cpg_pll_clk_set_rate()
111 return -EBUSY; in cpg_pll_clk_set_rate()
113 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI, in cpg_pll_clk_set_rate()
114 FIELD_PREP(CPG_PLLxCR0_NI, mult - 1)); in cpg_pll_clk_set_rate()
118 * clock change completion. in cpg_pll_clk_set_rate()
120 cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK); in cpg_pll_clk_set_rate()
131 return readl_poll_timeout(pll_clk->pllecr_reg, val, in cpg_pll_clk_set_rate()
132 val & pll_clk->pllecr_pllst_mask, 0, 1000); in cpg_pll_clk_set_rate()
155 return ERR_PTR(-ENOMEM); in cpg_pll_clk_register()
162 pll_clk->hw.init = &init; in cpg_pll_clk_register()
163 pll_clk->pllcr0_reg = base + cr0_offset; in cpg_pll_clk_register()
164 pll_clk->pllecr_reg = base + CPG_PLLECR; in cpg_pll_clk_register()
165 pll_clk->pllecr_pllst_mask = CPG_PLLECR_PLLST(index); in cpg_pll_clk_register()
169 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_SSMODE, 0); in cpg_pll_clk_register()
171 clk = clk_register(NULL, &pll_clk->hw); in cpg_pll_clk_register()
178 * Z0 Clock & Z1 Clock
199 unsigned int mult; in cpg_z_clk_recalc_rate() local
202 val = readl(zclk->reg) & zclk->mask; in cpg_z_clk_recalc_rate()
203 mult = 32 - (val >> __ffs(zclk->mask)); in cpg_z_clk_recalc_rate()
205 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, in cpg_z_clk_recalc_rate()
206 32 * zclk->fixed_div); in cpg_z_clk_recalc_rate()
213 unsigned int min_mult, max_mult, mult; in cpg_z_clk_determine_rate() local
216 rate = min(req->rate, req->max_rate); in cpg_z_clk_determine_rate()
217 if (rate <= zclk->max_rate) { in cpg_z_clk_determine_rate()
219 prate = zclk->max_rate; in cpg_z_clk_determine_rate()
224 req->best_parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), in cpg_z_clk_determine_rate()
225 prate * zclk->fixed_div); in cpg_z_clk_determine_rate()
227 prate = req->best_parent_rate / zclk->fixed_div; in cpg_z_clk_determine_rate()
228 min_mult = max(div64_ul(req->min_rate * 32ULL, prate), 1ULL); in cpg_z_clk_determine_rate()
229 max_mult = min(div64_ul(req->max_rate * 32ULL, prate), 32ULL); in cpg_z_clk_determine_rate()
231 return -EINVAL; in cpg_z_clk_determine_rate()
233 mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL, prate); in cpg_z_clk_determine_rate()
234 mult = clamp(mult, min_mult, max_mult); in cpg_z_clk_determine_rate()
236 req->rate = DIV_ROUND_CLOSEST_ULL((u64)prate * mult, 32); in cpg_z_clk_determine_rate()
244 unsigned int mult; in cpg_z_clk_set_rate() local
247 mult = DIV64_U64_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, in cpg_z_clk_set_rate()
249 mult = clamp(mult, 1U, 32U); in cpg_z_clk_set_rate()
251 if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) in cpg_z_clk_set_rate()
252 return -EBUSY; in cpg_z_clk_set_rate()
254 cpg_reg_modify(zclk->reg, zclk->mask, (32 - mult) << __ffs(zclk->mask)); in cpg_z_clk_set_rate()
258 * clock change completion. in cpg_z_clk_set_rate()
260 cpg_reg_modify(zclk->kick_reg, 0, CPG_FRQCRB_KICK); in cpg_z_clk_set_rate()
271 for (i = 1000; i; i--) { in cpg_z_clk_set_rate()
272 if (!(readl(zclk->kick_reg) & CPG_FRQCRB_KICK)) in cpg_z_clk_set_rate()
278 return -ETIMEDOUT; in cpg_z_clk_set_rate()
299 return ERR_PTR(-ENOMEM); in cpg_z_clk_register()
307 zclk->reg = reg + CPG_FRQCRC; in cpg_z_clk_register()
308 zclk->kick_reg = reg + CPG_FRQCRB; in cpg_z_clk_register()
309 zclk->hw.init = &init; in cpg_z_clk_register()
310 zclk->mask = GENMASK(offset + 4, offset); in cpg_z_clk_register()
311 zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ in cpg_z_clk_register()
313 clk = clk_register(NULL, &zclk->hw); in cpg_z_clk_register()
319 zclk->max_rate = clk_hw_get_rate(clk_hw_get_parent(&zclk->hw)) / in cpg_z_clk_register()
320 zclk->fixed_div; in cpg_z_clk_register()
337 unsigned int mult = 1; in rcar_gen4_cpg_clk_register() local
341 parent = clks[core->parent & 0xffff]; /* some types use high bits */ in rcar_gen4_cpg_clk_register()
345 switch (core->type) { in rcar_gen4_cpg_clk_register()
347 div = cpg_pll_config->extal_div; in rcar_gen4_cpg_clk_register()
351 mult = cpg_pll_config->pll1_mult; in rcar_gen4_cpg_clk_register()
352 div = cpg_pll_config->pll1_div; in rcar_gen4_cpg_clk_register()
357 * PLL2 is implemented as a custom clock, to change the in rcar_gen4_cpg_clk_register()
361 return cpg_pll_clk_register(core->name, __clk_get_name(parent), in rcar_gen4_cpg_clk_register()
365 mult = cpg_pll_config->pll2_mult; in rcar_gen4_cpg_clk_register()
366 div = cpg_pll_config->pll2_div; in rcar_gen4_cpg_clk_register()
370 mult = cpg_pll_config->pll3_mult; in rcar_gen4_cpg_clk_register()
371 div = cpg_pll_config->pll3_div; in rcar_gen4_cpg_clk_register()
375 mult = cpg_pll_config->pll4_mult; in rcar_gen4_cpg_clk_register()
376 div = cpg_pll_config->pll4_div; in rcar_gen4_cpg_clk_register()
380 mult = cpg_pll_config->pll5_mult; in rcar_gen4_cpg_clk_register()
381 div = cpg_pll_config->pll5_div; in rcar_gen4_cpg_clk_register()
385 mult = cpg_pll_config->pll6_mult; in rcar_gen4_cpg_clk_register()
386 div = cpg_pll_config->pll6_div; in rcar_gen4_cpg_clk_register()
390 value = readl(base + core->offset); in rcar_gen4_cpg_clk_register()
391 mult = (((value >> 24) & 0x7f) + 1) * 2; in rcar_gen4_cpg_clk_register()
395 return cpg_z_clk_register(core->name, __clk_get_name(parent), in rcar_gen4_cpg_clk_register()
396 base, core->div, core->offset); in rcar_gen4_cpg_clk_register()
403 return cpg_sdh_clk_register(core->name, base + core->offset, in rcar_gen4_cpg_clk_register()
407 return cpg_sd_clk_register(core->name, base + core->offset, in rcar_gen4_cpg_clk_register()
412 * Clock selectable between two parents and two fixed dividers in rcar_gen4_cpg_clk_register()
415 if (cpg_mode & BIT(core->offset)) { in rcar_gen4_cpg_clk_register()
416 div = core->div & 0xffff; in rcar_gen4_cpg_clk_register()
418 parent = clks[core->parent >> 16]; in rcar_gen4_cpg_clk_register()
421 div = core->div >> 16; in rcar_gen4_cpg_clk_register()
423 mult = 1; in rcar_gen4_cpg_clk_register()
428 * Clock combining OSC EXTAL predivider and a fixed divider in rcar_gen4_cpg_clk_register()
430 div = cpg_pll_config->osc_prediv * core->div; in rcar_gen4_cpg_clk_register()
434 return clk_register_divider_table(NULL, core->name, in rcar_gen4_cpg_clk_register()
441 return cpg_rpc_clk_register(core->name, base + CPG_RPCCKCR, in rcar_gen4_cpg_clk_register()
445 return cpg_rpcd2_clk_register(core->name, base + CPG_RPCCKCR, in rcar_gen4_cpg_clk_register()
449 return ERR_PTR(-EINVAL); in rcar_gen4_cpg_clk_register()
452 return clk_register_fixed_factor(NULL, core->name, in rcar_gen4_cpg_clk_register()
453 __clk_get_name(parent), 0, mult, div); in rcar_gen4_cpg_clk_register()