Lines Matching +full:pre +full:- +full:set
1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
26 * [0] - I/O port base address
63 #define S526_DIO_CTRL_GRP2_NEG BIT(8) /* irq on DIO[4-7] neg/pos edge */
68 #define S526_INT_CNTR(x) BIT(3 + (3 - ((x) & 0x3)))
106 /* if count direction control set to quadrature */
111 /* if count direction control set to software control */
118 /* if count direction control set to software control */
133 /* Control/Status - R = readable, W = writeable, C = write 1 to clear */
179 outw((val >> 16) & 0xffff, dev->iobase + S526_GPCT_MSB_REG(chan)); in s526_gpct_write()
180 outw(val & 0xffff, dev->iobase + S526_GPCT_LSB_REG(chan)); in s526_gpct_write()
189 val = inw(dev->iobase + S526_GPCT_LSB_REG(chan)) & 0xffff; in s526_gpct_read()
190 val |= (inw(dev->iobase + S526_GPCT_MSB_REG(chan)) & 0xff) << 16; in s526_gpct_read()
200 unsigned int chan = CR_CHAN(insn->chanspec); in s526_gpct_rinsn()
203 for (i = 0; i < insn->n; i++) in s526_gpct_rinsn()
206 return insn->n; in s526_gpct_rinsn()
214 struct s526_private *devpriv = dev->private; in s526_gpct_insn_config()
215 unsigned int chan = CR_CHAN(insn->chanspec); in s526_gpct_insn_config()
227 * data[2]: Pre-load Register Value in s526_gpct_insn_config()
230 devpriv->gpct_config[chan] = data[0]; in s526_gpct_insn_config()
233 /* Set Counter Mode Register */ in s526_gpct_insn_config()
235 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
242 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
246 * dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
274 /* Set Counter Mode Register */ in s526_gpct_insn_config()
276 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
278 /* Load the pre-load register */ in s526_gpct_insn_config()
284 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
291 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
294 dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
303 * data[2]: Pre-load Register 0 Value in s526_gpct_insn_config()
304 * data[3]: Pre-load Register 1 Value in s526_gpct_insn_config()
307 devpriv->gpct_config[chan] = data[0]; in s526_gpct_insn_config()
309 /* Set Counter Mode Register */ in s526_gpct_insn_config()
314 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
316 /* Load the pre-load register 0 */ in s526_gpct_insn_config()
319 /* Set Counter Mode Register */ in s526_gpct_insn_config()
324 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
326 /* Load the pre-load register 1 */ in s526_gpct_insn_config()
332 outw(val, dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
340 * data[2]: Pre-load Register 0 Value in s526_gpct_insn_config()
341 * data[3]: Pre-load Register 1 Value in s526_gpct_insn_config()
344 devpriv->gpct_config[chan] = data[0]; in s526_gpct_insn_config()
346 /* Set Counter Mode Register */ in s526_gpct_insn_config()
351 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
353 /* Load the pre-load register 0 */ in s526_gpct_insn_config()
356 /* Set Counter Mode Register */ in s526_gpct_insn_config()
361 outw(val, dev->iobase + S526_GPCT_MODE_REG(chan)); in s526_gpct_insn_config()
363 /* Load the pre-load register 1 */ in s526_gpct_insn_config()
369 outw(val, dev->iobase + S526_GPCT_CTRL_REG(chan)); in s526_gpct_insn_config()
374 return -EINVAL; in s526_gpct_insn_config()
377 return insn->n; in s526_gpct_insn_config()
385 struct s526_private *devpriv = dev->private; in s526_gpct_winsn()
386 unsigned int chan = CR_CHAN(insn->chanspec); in s526_gpct_winsn()
388 inw(dev->iobase + S526_GPCT_MODE_REG(chan)); /* Is this required? */ in s526_gpct_winsn()
391 switch (devpriv->gpct_config[chan]) { in s526_gpct_winsn()
396 * @pre PULSE_PERIOD > PULSE_WIDTH > 0 in s526_gpct_winsn()
401 return -EINVAL; in s526_gpct_winsn()
410 return -EINVAL; in s526_gpct_winsn()
413 return insn->n; in s526_gpct_winsn()
423 status = inw(dev->iobase + S526_INT_STATUS_REG); in s526_eoc()
426 outw(context, dev->iobase + S526_INT_STATUS_REG); in s526_eoc()
429 return -EBUSY; in s526_eoc()
437 struct s526_private *devpriv = dev->private; in s526_ai_insn_read()
438 unsigned int chan = CR_CHAN(insn->chanspec); in s526_ai_insn_read()
446 if (ctrl != devpriv->ai_ctrl) { in s526_ai_insn_read()
451 devpriv->ai_ctrl = ctrl; in s526_ai_insn_read()
455 for (i = 0; i < insn->n; i++) { in s526_ai_insn_read()
457 outw(ctrl, dev->iobase + S526_AI_CTRL_REG); in s526_ai_insn_read()
465 val = inw(dev->iobase + S526_AI_REG); in s526_ai_insn_read()
469 return insn->n; in s526_ai_insn_read()
477 unsigned int chan = CR_CHAN(insn->chanspec); in s526_ao_insn_write()
479 unsigned int val = s->readback[chan]; in s526_ao_insn_write()
483 outw(ctrl, dev->iobase + S526_AO_CTRL_REG); in s526_ao_insn_write()
486 for (i = 0; i < insn->n; i++) { in s526_ao_insn_write()
488 outw(val, dev->iobase + S526_AO_REG); in s526_ao_insn_write()
489 outw(ctrl, dev->iobase + S526_AO_CTRL_REG); in s526_ao_insn_write()
496 s->readback[chan] = val; in s526_ao_insn_write()
498 return insn->n; in s526_ao_insn_write()
507 outw(s->state, dev->iobase + S526_DIO_CTRL_REG); in s526_dio_insn_bits()
509 data[1] = inw(dev->iobase + S526_DIO_CTRL_REG) & 0xff; in s526_dio_insn_bits()
511 return insn->n; in s526_dio_insn_bits()
519 unsigned int chan = CR_CHAN(insn->chanspec); in s526_dio_insn_config()
525 * groups of 4; DIO group 1 (DIO0-3) and DIO group 2 (DIO4-7). in s526_dio_insn_config()
536 if (s->io_bits & 0x0f) in s526_dio_insn_config()
537 s->state |= S526_DIO_CTRL_GRP1_OUT; in s526_dio_insn_config()
539 s->state &= ~S526_DIO_CTRL_GRP1_OUT; in s526_dio_insn_config()
540 if (s->io_bits & 0xf0) in s526_dio_insn_config()
541 s->state |= S526_DIO_CTRL_GRP2_OUT; in s526_dio_insn_config()
543 s->state &= ~S526_DIO_CTRL_GRP2_OUT; in s526_dio_insn_config()
545 outw(s->state, dev->iobase + S526_DIO_CTRL_REG); in s526_dio_insn_config()
547 return insn->n; in s526_dio_insn_config()
556 ret = comedi_request_region(dev, it->options[0], 0x40); in s526_attach()
562 return -ENOMEM; in s526_attach()
568 /* General-Purpose Counter/Timer (GPCT) */ in s526_attach()
569 s = &dev->subdevices[0]; in s526_attach()
570 s->type = COMEDI_SUBD_COUNTER; in s526_attach()
571 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; in s526_attach()
572 s->n_chan = 4; in s526_attach()
573 s->maxdata = 0x00ffffff; in s526_attach()
574 s->insn_read = s526_gpct_rinsn; in s526_attach()
575 s->insn_config = s526_gpct_insn_config; in s526_attach()
576 s->insn_write = s526_gpct_winsn; in s526_attach()
584 s = &dev->subdevices[1]; in s526_attach()
585 s->type = COMEDI_SUBD_AI; in s526_attach()
586 s->subdev_flags = SDF_READABLE | SDF_DIFF; in s526_attach()
587 s->n_chan = 10; in s526_attach()
588 s->maxdata = 0xffff; in s526_attach()
589 s->range_table = &range_bipolar10; in s526_attach()
590 s->len_chanlist = 16; in s526_attach()
591 s->insn_read = s526_ai_insn_read; in s526_attach()
594 s = &dev->subdevices[2]; in s526_attach()
595 s->type = COMEDI_SUBD_AO; in s526_attach()
596 s->subdev_flags = SDF_WRITABLE; in s526_attach()
597 s->n_chan = 4; in s526_attach()
598 s->maxdata = 0xffff; in s526_attach()
599 s->range_table = &range_bipolar10; in s526_attach()
600 s->insn_write = s526_ao_insn_write; in s526_attach()
607 s = &dev->subdevices[3]; in s526_attach()
608 s->type = COMEDI_SUBD_DIO; in s526_attach()
609 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; in s526_attach()
610 s->n_chan = 8; in s526_attach()
611 s->maxdata = 1; in s526_attach()
612 s->range_table = &range_digital; in s526_attach()
613 s->insn_bits = s526_dio_insn_bits; in s526_attach()
614 s->insn_config = s526_dio_insn_config; in s526_attach()
628 MODULE_DESCRIPTION("Comedi low-level driver");