Lines Matching +full:system +full:- +full:cache +full:- +full:controller

1 # SPDX-License-Identifier: GPL-2.0-only
14 	  Support for PMU events monitoring on the ARM CCI (Cache Coherent
17 	  If compiled as a module, it will be called arm-cci.
20 	bool "support CCI-400"
25 	  CCI-400 provides 4 independent event counters counting events related
29 	bool "support CCI-500/CCI-550"
33 	  CCI-500/CCI-550 both provide 8 independent event counters, which can
41 	  PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
45 	tristate "Arm CMN-600 PMU support"
48 	  Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 	  Say y if you want to use CPU performance monitors on ARM-based
61 	bool "RISC-V PMU framework"
64 	  Say y if you want to use CPU performance monitors on RISCV-based
71 	bool "RISC-V legacy PMU implementation"
75 	  implementation on RISC-V based systems. This only allows counting
81 	bool "RISC-V PMU based on SBI PMU extension"
85 	  using SBI PMU extension on RISC-V based systems. This option provides
119 	  system, control logic. The PMU allows counting various events related
139 	bool "Qualcomm Technologies L2-cache PMU"
143 	  Provides support for the L2 cache performance monitor unit (PMU)
145 	  Adds the L2 cache PMU into the perf events subsystem for
146 	  monitoring L2 cache events.
149 	bool "Qualcomm Technologies L3-cache PMU"
153 	   Provides support for the L3 cache performance monitor unit (PMU)
155 	   Adds the L3 cache PMU into the perf events subsystem for
156 	   monitoring L3 cache events.
165 	   The SoC has PMU support in its L3 cache controller (L3C) and
166 	   in the DDR4 Memory Controller (DMC).
170         bool "APM X-Gene SoC PMU"
173           Say y if you want to use APM X-Gene SoC performance monitors.
184 	tristate "Enable PMU support for the ARM DMC-620 memory controller"
187 	  Support for PMU events monitoring on the ARM DMC-620 memory
188 	  controller.
191 	tristate "Marvell CN10K LLC-TAD PMU"
194 	  Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
201 	  Provides support for the non-architectural CPU PMUs present on
205 	tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"
209 	  Sub-system.