Lines Matching +full:spe +full:- +full:pmu

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/include/asm/pmu.h
20  * The ARMv7 CPU PMU supports up to 32 event counters.
25  * ARM PMU hw_event flags
40 	[0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
43 [0 ... C(MAX) - 1] = {							\
44 	[0 ... C(OP_MAX) - 1] = {					\
45 		[0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,	\
49 /* The events for a given PMU register set. */
52 	 * The events that are active on the PMU for the given index.
63 	 * Hardware lock to serialize accesses to PMU registers. Needed for the
86 	struct pmu	pmu;  member
90 	irqreturn_t	(*handle_irq)(struct arm_pmu *pmu);
106 	bool		secure_access; /* 32-bit ARM only */
115 	/* the attr_groups array must be NULL-terminated */
124 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
171 void kvm_host_pmu_init(struct arm_pmu *pmu);
180 void armpmu_free(struct arm_pmu *pmu);
181 int armpmu_register(struct arm_pmu *pmu);
185 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
189 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1"