Lines Matching full:nir
23 #include "nir/nir.h"
24 #include "nir/nir_xfb_info.h"
37 gather_intrinsic_load_input_info(const nir_shader *nir, const nir_intrinsic_instr *instr, in gather_intrinsic_load_input_info() argument
40 switch (nir->info.stage) { in gather_intrinsic_load_input_info()
55 gather_intrinsic_store_output_info(const nir_shader *nir, const nir_intrinsic_instr *instr, in gather_intrinsic_store_output_info() argument
67 switch (nir->info.stage) { in gather_intrinsic_store_output_info()
89 gather_push_constant_info(const nir_shader *nir, const nir_intrinsic_instr *instr, in gather_push_constant_info() argument
108 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, in gather_intrinsic_info() argument
167 gather_push_constant_info(nir, instr, info); in gather_intrinsic_info()
195 gather_intrinsic_load_input_info(nir, instr, info); in gather_intrinsic_info()
198 gather_intrinsic_store_output_info(nir, instr, info); in gather_intrinsic_info()
212 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr, struct radv_shader_info *info) in gather_tex_info() argument
229 gather_info_block(const nir_shader *nir, const nir_block *block, struct radv_shader_info *info) in gather_info_block() argument
234 gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info); in gather_info_block()
237 gather_tex_info(nir, nir_instr_as_tex(instr), info); in gather_info_block()
246 gather_info_input_decl_vs(const nir_shader *nir, const nir_variable *var, in gather_info_input_decl_vs() argument
288 gather_info_input_decl_ps(const nir_shader *nir, const nir_variable *var, in gather_info_input_decl_ps() argument
328 gather_info_input_decl(const nir_shader *nir, const nir_variable *var, in gather_info_input_decl() argument
331 switch (nir->info.stage) { in gather_info_input_decl()
333 gather_info_input_decl_vs(nir, var, key, info); in gather_info_input_decl()
336 gather_info_input_decl_ps(nir, var, info); in gather_info_input_decl()
344 gather_info_output_decl_gs(const nir_shader *nir, const nir_variable *var, in gather_info_output_decl_gs() argument
358 get_vs_output_info(const nir_shader *nir, struct radv_shader_info *info) in get_vs_output_info() argument
361 switch (nir->info.stage) { in get_vs_output_info()
383 gather_info_output_decl(const nir_shader *nir, const nir_variable *var, in gather_info_output_decl() argument
386 switch (nir->info.stage) { in gather_info_output_decl()
390 gather_info_output_decl_gs(nir, var, info); in gather_info_output_decl()
400 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info) in gather_xfb_info() argument
404 if (!nir->xfb_info) in gather_xfb_info()
407 const nir_xfb_info *xfb = nir->xfb_info; in gather_xfb_info()
457 radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir, in radv_nir_shader_info_pass() argument
462 struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); in radv_nir_shader_info_pass()
465 (layout->dynamic_shader_stages & mesa_to_vk_shader_stage(nir->info.stage))) { in radv_nir_shader_info_pass()
470 if (nir->info.stage == MESA_SHADER_VERTEX) { in radv_nir_shader_info_pass()
471 if (pipeline_key->vs.dynamic_input_state && nir->info.inputs_read) { in radv_nir_shader_info_pass()
482 if (nir->info.stage == MESA_SHADER_FRAGMENT) { in radv_nir_shader_info_pass()
494 nir_foreach_shader_in_variable (variable, nir) in radv_nir_shader_info_pass()
495 gather_info_input_decl(nir, variable, pipeline_key, info); in radv_nir_shader_info_pass()
498 gather_info_block(nir, block, info); in radv_nir_shader_info_pass()
501 nir_foreach_shader_out_variable(variable, nir) gather_info_output_decl(nir, variable, info); in radv_nir_shader_info_pass()
503 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL || in radv_nir_shader_info_pass()
504 nir->info.stage == MESA_SHADER_GEOMETRY) in radv_nir_shader_info_pass()
505 gather_xfb_info(nir, info); in radv_nir_shader_info_pass()
507 struct radv_vs_output_info *outinfo = get_vs_output_info(nir, info); in radv_nir_shader_info_pass()
514 nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask; in radv_nir_shader_info_pass()
516 nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask; in radv_nir_shader_info_pass()
519 if (nir->info.stage == MESA_SHADER_MESH && pipeline_key->has_multiview_view_index) { in radv_nir_shader_info_pass()
536 outinfo->clip_dist_mask = (1 << nir->info.clip_distance_array_size) - 1; in radv_nir_shader_info_pass()
537 outinfo->cull_dist_mask = (1 << nir->info.cull_distance_array_size) - 1; in radv_nir_shader_info_pass()
538 outinfo->cull_dist_mask <<= nir->info.clip_distance_array_size; in radv_nir_shader_info_pass()
580 if (nir->info.stage == MESA_SHADER_FRAGMENT) { in radv_nir_shader_info_pass()
581 uint64_t per_primitive_input_mask = nir->info.inputs_read & nir->info.per_primitive_inputs; in radv_nir_shader_info_pass()
583 assert(num_per_primitive_inputs <= nir->num_inputs); in radv_nir_shader_info_pass()
585 info->ps.num_interp = nir->num_inputs - num_per_primitive_inputs; in radv_nir_shader_info_pass()
589 info->vs.needs_draw_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); in radv_nir_shader_info_pass()
590 …info->vs.needs_base_instance |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTAN… in radv_nir_shader_info_pass()
591 … info->vs.needs_instance_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID); in radv_nir_shader_info_pass()
592 info->uses_view_index |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VIEW_INDEX); in radv_nir_shader_info_pass()
593 … info->uses_invocation_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID); in radv_nir_shader_info_pass()
594 info->uses_prim_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); in radv_nir_shader_info_pass()
597 info->cs.uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORKGROUPS); in radv_nir_shader_info_pass()
598 …info->cs.uses_local_invocation_idx = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_… in radv_nir_shader_info_pass()
599 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) | in radv_nir_shader_info_pass()
600 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS); in radv_nir_shader_info_pass()
601 switch (nir->info.stage) { in radv_nir_shader_info_pass()
605 info->cs.block_size[i] = nir->info.workgroup_size[i]; in radv_nir_shader_info_pass()
606 …info->cs.uses_ray_launch_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_RAY_LAUNCH_… in radv_nir_shader_info_pass()
611 if (nir->info.stage == MESA_SHADER_TASK) { in radv_nir_shader_info_pass()
614 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_WORKGROUP_ID); in radv_nir_shader_info_pass()
627 info->ps.can_discard = nir->info.fs.uses_discard; in radv_nir_shader_info_pass()
628 info->ps.early_fragment_test = nir->info.fs.early_fragment_tests; in radv_nir_shader_info_pass()
629 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage; in radv_nir_shader_info_pass()
630 info->ps.depth_layout = nir->info.fs.depth_layout; in radv_nir_shader_info_pass()
631 info->ps.uses_sample_shading = nir->info.fs.uses_sample_shading; in radv_nir_shader_info_pass()
632 info->ps.writes_memory = nir->info.writes_memory; in radv_nir_shader_info_pass()
633 info->ps.has_pcoord = nir->info.inputs_read & VARYING_BIT_PNTC; in radv_nir_shader_info_pass()
634 info->ps.prim_id_input = nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID; in radv_nir_shader_info_pass()
635 info->ps.layer_input = nir->info.inputs_read & VARYING_BIT_LAYER; in radv_nir_shader_info_pass()
636 info->ps.viewport_index_input = nir->info.inputs_read & VARYING_BIT_VIEWPORT; in radv_nir_shader_info_pass()
637 info->ps.writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH); in radv_nir_shader_info_pass()
638 info->ps.writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL); in radv_nir_shader_info_pass()
639 … info->ps.writes_sample_mask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK); in radv_nir_shader_info_pass()
640 …info->ps.reads_sample_mask_in = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK… in radv_nir_shader_info_pass()
641 info->ps.reads_sample_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID); in radv_nir_shader_info_pass()
642 …info->ps.reads_frag_shading_rate = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_SHA… in radv_nir_shader_info_pass()
643 … info->ps.reads_front_face = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE); in radv_nir_shader_info_pass()
644 …info->ps.reads_barycentric_model = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENT… in radv_nir_shader_info_pass()
647 info->gs.vertices_in = nir->info.gs.vertices_in; in radv_nir_shader_info_pass()
648 info->gs.vertices_out = nir->info.gs.vertices_out; in radv_nir_shader_info_pass()
649 info->gs.output_prim = nir->info.gs.output_primitive; in radv_nir_shader_info_pass()
650 info->gs.invocations = nir->info.gs.invocations; in radv_nir_shader_info_pass()
652 nir->info.gs.active_stream_mask ? util_last_bit(nir->info.gs.active_stream_mask) - 1 : 0; in radv_nir_shader_info_pass()
655 info->tes._primitive_mode = nir->info.tess._primitive_mode; in radv_nir_shader_info_pass()
656 info->tes.spacing = nir->info.tess.spacing; in radv_nir_shader_info_pass()
657 info->tes.ccw = nir->info.tess.ccw; in radv_nir_shader_info_pass()
658 info->tes.point_mode = nir->info.tess.point_mode; in radv_nir_shader_info_pass()
661 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; in radv_nir_shader_info_pass()
666 info->ms.output_prim = nir->info.mesh.primitive_type; in radv_nir_shader_info_pass()
672 if (nir->info.stage == MESA_SHADER_GEOMETRY) { in radv_nir_shader_info_pass()
674 nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4; in radv_nir_shader_info_pass()
675 info->gs.gsvs_vertex_size = (util_bitcount64(nir->info.outputs_written) + add_clip) * 16; in radv_nir_shader_info_pass()
676 info->gs.max_gsvs_emit_size = info->gs.gsvs_vertex_size * nir->info.gs.vertices_out; in radv_nir_shader_info_pass()
680 if ((nir->info.stage == MESA_SHADER_VERTEX && info->vs.as_es) || in radv_nir_shader_info_pass()
681 (nir->info.stage == MESA_SHADER_TESS_EVAL && info->tes.as_es)) { in radv_nir_shader_info_pass()
683 nir->info.stage == MESA_SHADER_VERTEX ? &info->vs.es_info : &info->tes.es_info; in radv_nir_shader_info_pass()
684 uint32_t num_outputs_written = nir->info.stage == MESA_SHADER_VERTEX in radv_nir_shader_info_pass()
690 if (nir->info.stage == MESA_SHADER_FRAGMENT) { in radv_nir_shader_info_pass()
700 info->ps.writes_memory || nir->info.fs.needs_quad_helper_invocations || in radv_nir_shader_info_pass()
701 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) || in radv_nir_shader_info_pass()
702 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_POINT_COORD) || in radv_nir_shader_info_pass()
703 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) || in radv_nir_shader_info_pass()
704 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) || in radv_nir_shader_info_pass()
705 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) || in radv_nir_shader_info_pass()
706 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION)); in radv_nir_shader_info_pass()