1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 #ifndef _UAPI_KBASE_GPU_REGMAP_CSF_H_ 23 #define _UAPI_KBASE_GPU_REGMAP_CSF_H_ 24 25 #include <linux/types.h> 26 27 #if !MALI_USE_CSF && defined(__KERNEL__) 28 #error "Cannot be compiled with JM" 29 #endif 30 31 /* GPU_CONTROL_MCU base address */ 32 #define GPU_CONTROL_MCU_BASE 0x3000 33 34 /* MCU_SUBSYSTEM base address */ 35 #define MCU_SUBSYSTEM_BASE 0x20000 36 37 /* IPA control registers */ 38 #define IPA_CONTROL_BASE 0x40000 39 #define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE+(r)) 40 #define COMMAND 0x000 /* (WO) Command register */ 41 #define STATUS 0x004 /* (RO) Status register */ 42 #define TIMER 0x008 /* (RW) Timer control register */ 43 44 #define SELECT_CSHW_LO 0x010 /* (RW) Counter select for CS hardware, low word */ 45 #define SELECT_CSHW_HI 0x014 /* (RW) Counter select for CS hardware, high word */ 46 #define SELECT_MEMSYS_LO 0x018 /* (RW) Counter select for Memory system, low word */ 47 #define SELECT_MEMSYS_HI 0x01C /* (RW) Counter select for Memory system, high word */ 48 #define SELECT_TILER_LO 0x020 /* (RW) Counter select for Tiler cores, low word */ 49 #define SELECT_TILER_HI 0x024 /* (RW) Counter select for Tiler cores, high word */ 50 #define SELECT_SHADER_LO 0x028 /* (RW) Counter select for Shader cores, low word */ 51 #define SELECT_SHADER_HI 0x02C /* (RW) Counter select for Shader cores, high word */ 52 53 /* Accumulated counter values for CS hardware */ 54 #define VALUE_CSHW_BASE 0x100 55 #define VALUE_CSHW_REG_LO(n) (VALUE_CSHW_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */ 56 #define VALUE_CSHW_REG_HI(n) (VALUE_CSHW_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */ 57 58 /* Accumulated counter values for memory system */ 59 #define VALUE_MEMSYS_BASE 0x140 60 #define VALUE_MEMSYS_REG_LO(n) (VALUE_MEMSYS_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */ 61 #define VALUE_MEMSYS_REG_HI(n) (VALUE_MEMSYS_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */ 62 63 #define VALUE_TILER_BASE 0x180 64 #define VALUE_TILER_REG_LO(n) (VALUE_TILER_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */ 65 #define VALUE_TILER_REG_HI(n) (VALUE_TILER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */ 66 67 #define VALUE_SHADER_BASE 0x1C0 68 #define VALUE_SHADER_REG_LO(n) (VALUE_SHADER_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */ 69 #define VALUE_SHADER_REG_HI(n) (VALUE_SHADER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */ 70 71 /* Set to implementation defined, outer caching */ 72 #define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull 73 /* Set to write back memory, outer caching */ 74 #define AS_MEMATTR_AARCH64_OUTER_WA 0x8Dull 75 /* Set to inner non-cacheable, outer-non-cacheable 76 * Setting defined by the alloc bits is ignored, but set to a valid encoding: 77 * - no-alloc on read 78 * - no alloc on write 79 */ 80 #define AS_MEMATTR_AARCH64_NON_CACHEABLE 0x4Cull 81 /* Set to shared memory, that is inner cacheable on ACE and inner or outer 82 * shared, otherwise inner non-cacheable. 83 * Outer cacheable if inner or outer shared, otherwise outer non-cacheable. 84 */ 85 #define AS_MEMATTR_AARCH64_SHARED 0x8ull 86 87 /* Symbols for default MEMATTR to use 88 * Default is - HW implementation defined caching 89 */ 90 #define AS_MEMATTR_INDEX_DEFAULT 0 91 #define AS_MEMATTR_INDEX_DEFAULT_ACE 3 92 93 /* HW implementation defined caching */ 94 #define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0 95 /* Force cache on */ 96 #define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1 97 /* Write-alloc */ 98 #define AS_MEMATTR_INDEX_WRITE_ALLOC 2 99 /* Outer coherent, inner implementation defined policy */ 100 #define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3 101 /* Outer coherent, write alloc inner */ 102 #define AS_MEMATTR_INDEX_OUTER_WA 4 103 /* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */ 104 #define AS_MEMATTR_INDEX_NON_CACHEABLE 5 105 /* Normal memory, shared between MCU and Host */ 106 #define AS_MEMATTR_INDEX_SHARED 6 107 108 /* Configuration bits for the CSF. */ 109 #define CSF_CONFIG 0xF00 110 111 /* CSF_CONFIG register */ 112 #define CSF_CONFIG_FORCE_COHERENCY_FEATURES_SHIFT 2 113 114 /* GPU control registers */ 115 #define CORE_FEATURES 0x008 /* () Shader Core Features */ 116 #define MCU_CONTROL 0x700 117 #define MCU_STATUS 0x704 118 119 #define MCU_CNTRL_ENABLE (1 << 0) 120 #define MCU_CNTRL_AUTO (1 << 1) 121 #define MCU_CNTRL_DISABLE (0) 122 123 #define MCU_CNTRL_DOORBELL_DISABLE_SHIFT (31) 124 #define MCU_CNTRL_DOORBELL_DISABLE_MASK (1 << MCU_CNTRL_DOORBELL_DISABLE_SHIFT) 125 126 #define MCU_STATUS_HALTED (1 << 1) 127 128 #define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory 129 * region base address, low word 130 */ 131 #define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory 132 * region base address, high word 133 */ 134 #define PRFCNT_CONFIG 0x068 /* (RW) Performance counter 135 * configuration 136 */ 137 138 #define PRFCNT_CSHW_EN 0x06C /* (RW) Performance counter 139 * enable for CS Hardware 140 */ 141 142 #define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable 143 * flags for shader cores 144 */ 145 #define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable 146 * flags for tiler 147 */ 148 #define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable 149 * flags for MMU/L2 cache 150 */ 151 152 /* JOB IRQ flags */ 153 #define JOB_IRQ_GLOBAL_IF (1 << 31) /* Global interface interrupt received */ 154 155 /* GPU_COMMAND codes */ 156 #define GPU_COMMAND_CODE_NOP 0x00 /* No operation, nothing happens */ 157 #define GPU_COMMAND_CODE_RESET 0x01 /* Reset the GPU */ 158 #define GPU_COMMAND_CODE_PRFCNT 0x02 /* Clear or sample performance counters */ 159 #define GPU_COMMAND_CODE_TIME 0x03 /* Configure time sources */ 160 #define GPU_COMMAND_CODE_FLUSH_CACHES 0x04 /* Flush caches */ 161 #define GPU_COMMAND_CODE_SET_PROTECTED_MODE 0x05 /* Places the GPU in protected mode */ 162 #define GPU_COMMAND_CODE_FINISH_HALT 0x06 /* Halt CSF */ 163 #define GPU_COMMAND_CODE_CLEAR_FAULT 0x07 /* Clear GPU_FAULTSTATUS and GPU_FAULTADDRESS, TODX */ 164 165 /* GPU_COMMAND_RESET payloads */ 166 167 /* This will leave the state of active jobs UNDEFINED, but will leave the external bus in a defined and idle state. 168 * Power domains will remain powered on. 169 */ 170 #define GPU_COMMAND_RESET_PAYLOAD_FAST_RESET 0x00 171 172 /* This will leave the state of active CSs UNDEFINED, but will leave the external bus in a defined and 173 * idle state. 174 */ 175 #define GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET 0x01 176 177 /* This reset will leave the state of currently active streams UNDEFINED, will likely lose data, and may leave 178 * the system bus in an inconsistent state. Use only as a last resort when nothing else works. 179 */ 180 #define GPU_COMMAND_RESET_PAYLOAD_HARD_RESET 0x02 181 182 /* GPU_COMMAND_PRFCNT payloads */ 183 #define GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE 0x01 /* Sample performance counters */ 184 #define GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR 0x02 /* Clear performance counters */ 185 186 /* GPU_COMMAND_TIME payloads */ 187 #define GPU_COMMAND_TIME_DISABLE 0x00 /* Disable cycle counter */ 188 #define GPU_COMMAND_TIME_ENABLE 0x01 /* Enable cycle counter */ 189 190 /* GPU_COMMAND_FLUSH_CACHES payloads bits for L2 caches */ 191 #define GPU_COMMAND_FLUSH_PAYLOAD_L2_NONE 0x000 /* No flush */ 192 #define GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN 0x001 /* CLN only */ 193 #define GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE 0x003 /* CLN + INV */ 194 195 /* GPU_COMMAND_FLUSH_CACHES payloads bits for Load-store caches */ 196 #define GPU_COMMAND_FLUSH_PAYLOAD_LSC_NONE 0x000 /* No flush */ 197 #define GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN 0x010 /* CLN only */ 198 #define GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN_INVALIDATE 0x030 /* CLN + INV */ 199 200 /* GPU_COMMAND_FLUSH_CACHES payloads bits for Other caches */ 201 #define GPU_COMMAND_FLUSH_PAYLOAD_OTHER_NONE 0x000 /* No flush */ 202 #define GPU_COMMAND_FLUSH_PAYLOAD_OTHER_INVALIDATE 0x200 /* INV only */ 203 204 /* GPU_COMMAND command + payload */ 205 #define GPU_COMMAND_CODE_PAYLOAD(opcode, payload) \ 206 ((__u32)opcode | ((__u32)payload << 8)) 207 208 /* Final GPU_COMMAND form */ 209 /* No operation, nothing happens */ 210 #define GPU_COMMAND_NOP \ 211 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_NOP, 0) 212 213 /* Stop all external bus interfaces, and then reset the entire GPU. */ 214 #define GPU_COMMAND_SOFT_RESET \ 215 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET) 216 217 /* Immediately reset the entire GPU. */ 218 #define GPU_COMMAND_HARD_RESET \ 219 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_HARD_RESET) 220 221 /* Clear all performance counters, setting them all to zero. */ 222 #define GPU_COMMAND_PRFCNT_CLEAR \ 223 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR) 224 225 /* Sample all performance counters, writing them out to memory */ 226 #define GPU_COMMAND_PRFCNT_SAMPLE \ 227 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE) 228 229 /* Starts the cycle counter, and system timestamp propagation */ 230 #define GPU_COMMAND_CYCLE_COUNT_START \ 231 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_ENABLE) 232 233 /* Stops the cycle counter, and system timestamp propagation */ 234 #define GPU_COMMAND_CYCLE_COUNT_STOP \ 235 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_DISABLE) 236 237 /* Clean and invalidate L2 cache (Equivalent to FLUSH_PT) */ 238 #define GPU_COMMAND_CACHE_CLN_INV_L2 \ 239 GPU_COMMAND_CODE_PAYLOAD( \ 240 GPU_COMMAND_CODE_FLUSH_CACHES, \ 241 (GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE | \ 242 GPU_COMMAND_FLUSH_PAYLOAD_LSC_NONE | \ 243 GPU_COMMAND_FLUSH_PAYLOAD_OTHER_NONE)) 244 245 /* Clean and invalidate L2 and LSC caches (Equivalent to FLUSH_MEM) */ 246 #define GPU_COMMAND_CACHE_CLN_INV_L2_LSC \ 247 GPU_COMMAND_CODE_PAYLOAD( \ 248 GPU_COMMAND_CODE_FLUSH_CACHES, \ 249 (GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE | \ 250 GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN_INVALIDATE | \ 251 GPU_COMMAND_FLUSH_PAYLOAD_OTHER_NONE)) 252 253 /* Clean and invalidate L2, LSC, and Other caches */ 254 #define GPU_COMMAND_CACHE_CLN_INV_FULL \ 255 GPU_COMMAND_CODE_PAYLOAD( \ 256 GPU_COMMAND_CODE_FLUSH_CACHES, \ 257 (GPU_COMMAND_FLUSH_PAYLOAD_L2_CLEAN_INVALIDATE | \ 258 GPU_COMMAND_FLUSH_PAYLOAD_LSC_CLEAN_INVALIDATE | \ 259 GPU_COMMAND_FLUSH_PAYLOAD_OTHER_INVALIDATE)) 260 261 /* Merge cache flush commands */ 262 #define GPU_COMMAND_FLUSH_CACHE_MERGE(cmd1, cmd2) ((cmd1) | (cmd2)) 263 264 /* Places the GPU in protected mode */ 265 #define GPU_COMMAND_SET_PROTECTED_MODE \ 266 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_SET_PROTECTED_MODE, 0) 267 268 /* Halt CSF */ 269 #define GPU_COMMAND_FINISH_HALT \ 270 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FINISH_HALT, 0) 271 272 /* Clear GPU faults */ 273 #define GPU_COMMAND_CLEAR_FAULT \ 274 GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_CLEAR_FAULT, 0) 275 276 /* End Command Values */ 277 278 /* GPU_FAULTSTATUS register */ 279 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0 280 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFFul) 281 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \ 282 (((reg_val)&GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) \ 283 >> GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT) 284 #define GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT 8 285 #define GPU_FAULTSTATUS_ACCESS_TYPE_MASK \ 286 (0x3ul << GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT) 287 288 #define GPU_FAULTSTATUS_ADDR_VALID_SHIFT 10 289 #define GPU_FAULTSTATUS_ADDR_VALID_FLAG \ 290 (1ul << GPU_FAULTSTATUS_ADDR_VALID_SHIFT) 291 292 #define GPU_FAULTSTATUS_JASID_VALID_SHIFT 11 293 #define GPU_FAULTSTATUS_JASID_VALID_FLAG \ 294 (1ul << GPU_FAULTSTATUS_JASID_VALID_SHIFT) 295 296 #define GPU_FAULTSTATUS_JASID_SHIFT 12 297 #define GPU_FAULTSTATUS_JASID_MASK (0xF << GPU_FAULTSTATUS_JASID_SHIFT) 298 #define GPU_FAULTSTATUS_JASID_GET(reg_val) \ 299 (((reg_val)&GPU_FAULTSTATUS_JASID_MASK) >> GPU_FAULTSTATUS_JASID_SHIFT) 300 #define GPU_FAULTSTATUS_JASID_SET(reg_val, value) \ 301 (((reg_val) & ~GPU_FAULTSTATUS_JASID_MASK) | \ 302 (((value) << GPU_FAULTSTATUS_JASID_SHIFT) & GPU_FAULTSTATUS_JASID_MASK)) 303 304 #define GPU_FAULTSTATUS_SOURCE_ID_SHIFT 16 305 #define GPU_FAULTSTATUS_SOURCE_ID_MASK \ 306 (0xFFFFul << GPU_FAULTSTATUS_SOURCE_ID_SHIFT) 307 /* End GPU_FAULTSTATUS register */ 308 309 /* GPU_FAULTSTATUS_ACCESS_TYPE values */ 310 #define GPU_FAULTSTATUS_ACCESS_TYPE_ATOMIC 0x0 311 #define GPU_FAULTSTATUS_ACCESS_TYPE_EXECUTE 0x1 312 #define GPU_FAULTSTATUS_ACCESS_TYPE_READ 0x2 313 #define GPU_FAULTSTATUS_ACCESS_TYPE_WRITE 0x3 314 /* End of GPU_FAULTSTATUS_ACCESS_TYPE values */ 315 316 /* Implementation-dependent exception codes used to indicate CSG 317 * and CS errors that are not specified in the specs. 318 */ 319 #define GPU_EXCEPTION_TYPE_SW_FAULT_0 ((__u8)0x70) 320 #define GPU_EXCEPTION_TYPE_SW_FAULT_1 ((__u8)0x71) 321 #define GPU_EXCEPTION_TYPE_SW_FAULT_2 ((__u8)0x72) 322 323 /* GPU_FAULTSTATUS_EXCEPTION_TYPE values */ 324 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_OK 0x00 325 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_BUS_FAULT 0x80 326 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_SHAREABILITY_FAULT 0x88 327 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_SYSTEM_SHAREABILITY_FAULT 0x89 328 #define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_CACHEABILITY_FAULT 0x8A 329 /* End of GPU_FAULTSTATUS_EXCEPTION_TYPE values */ 330 331 #define GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT GPU_U(10) 332 #define GPU_FAULTSTATUS_ADDRESS_VALID_MASK (GPU_U(0x1) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) 333 #define GPU_FAULTSTATUS_ADDRESS_VALID_GET(reg_val) \ 334 (((reg_val)&GPU_FAULTSTATUS_ADDRESS_VALID_MASK) >> GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) 335 #define GPU_FAULTSTATUS_ADDRESS_VALID_SET(reg_val, value) \ 336 (((reg_val) & ~GPU_FAULTSTATUS_ADDRESS_VALID_MASK) | \ 337 (((value) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) & GPU_FAULTSTATUS_ADDRESS_VALID_MASK)) 338 339 /* IRQ flags */ 340 #define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */ 341 #define GPU_PROTECTED_FAULT (1 << 1) /* A GPU fault has occurred in protected mode */ 342 #define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */ 343 #define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */ 344 #define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */ 345 #define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */ 346 #define DOORBELL_MIRROR (1 << 18) /* Mirrors the doorbell interrupt line to the CPU */ 347 #define MCU_STATUS_GPU_IRQ (1 << 19) /* MCU requires attention */ 348 349 /* 350 * In Debug build, 351 * GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and unmask interupts sources of GPU_IRQ 352 * by writing it onto GPU_IRQ_CLEAR/MASK registers. 353 * 354 * In Release build, 355 * GPU_IRQ_REG_COMMON is used. 356 * 357 * Note: 358 * CLEAN_CACHES_COMPLETED - Used separately for cache operation. 359 * DOORBELL_MIRROR - Do not have it included for GPU_IRQ_REG_COMMON 360 * as it can't be cleared by GPU_IRQ_CLEAR, thus interrupt storm might happen 361 */ 362 #define GPU_IRQ_REG_COMMON (GPU_FAULT | GPU_PROTECTED_FAULT | RESET_COMPLETED \ 363 | POWER_CHANGED_ALL | MCU_STATUS_GPU_IRQ) 364 365 /* GPU_CONTROL_MCU.GPU_IRQ_RAWSTAT */ 366 #define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when performance count sample has completed */ 367 368 #endif /* _UAPI_KBASE_GPU_REGMAP_CSF_H_ */ 369