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Searched defs:CTRL (Results 1 – 25 of 29) sorted by relevance

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/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl/sysroot/usr/include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl_win/sysroot/usr/include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl/riscv32-linux-musl/sys-include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl_fp_win/riscv32-linux-musl/sys-include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/kernel/liteos/liteos_v208.5.0/Huawei_LiteOS/open_source/musl/include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl_fp_win/sysroot/usr/include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl_fp/sysroot/usr/include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl_fp/riscv32-linux-musl/sys-include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/tools/bin/compiler/riscv/cc_riscv32_musl_100/cc_riscv32_musl_win/riscv32-linux-musl/sys-include/sys/
Dttydefaults.h9 #define CTRL(x) ((x)&037) macro
/device/soc/hisilicon/ws63v100/sdk/kernel/liteos/liteos_v208.5.0/Huawei_LiteOS/open_source/CMSIS/CMSIS/Core/Include/
Dcore_cm0plus.h474 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
527 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_sc000.h490 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
543 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_armv8mbl.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
829 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
935 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm23.h562 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1010 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm0.h450 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_cm3.h708 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
848 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1158 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_sc300.h693 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1143 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm4.h766 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
906 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1216 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_cm1.h476 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_armv8mml.h967 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1119 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1405 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1517 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_starmc1.h1025 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1177 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1650 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm35p.h967 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1119 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1480 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1592 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm33.h967 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1119 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1480 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
1592 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member
Dcore_cm7.h990 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1130 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1443 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
Dcore_armv81mml.h1028 …__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
1181 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ member
1492 …__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ member
2283 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ member
2398 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ member

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