1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __VOU_DRV_H__ 20 #define __VOU_DRV_H__ 21 22 #include "hi_osal.h" 23 #include "hi_common_adapt.h" 24 #include "valg_plat.h" 25 #include "sys_ext.h" 26 #include "hi_comm_vo_adapt.h" 27 #include "mkp_vo_dev.h" 28 #include "vou_hal.h" 29 #include "vou_coef_org.h" 30 31 #ifdef __cplusplus 32 #if __cplusplus 33 extern "C" { 34 #endif 35 #endif /* end of #ifdef __cplusplus */ 36 37 #define VOU_INTCLEAR_ALL 0xffffffff 38 39 #define VO_MAX_VGS_JOB_CNT 1 40 41 typedef enum { 42 VO_INT_MODE_FRAME = 0x0, 43 VO_INT_MODE_FIELD = 0x1, 44 VO_INT_MODE_BUTT 45 } vo_int_mode; 46 47 typedef enum { 48 VO_LAYER_DDR0 = 0, 49 VO_LAYER_DDR1 = 1, 50 VO_LAYER_DDR_BUTT 51 } vo_layer_ddr; 52 53 /* vou mixer prio id */ 54 typedef enum { 55 VOU_MIX_PRIO0 = 0, 56 VOU_MIX_PRIO1, 57 VOU_MIX_PRIO2, 58 VOU_MIX_PRIO3, 59 VOU_MIX_PRIO4, 60 VOU_MIX_PRIO5, 61 VOU_MIX_PRIO_CLR, 62 VOU_MIX_BUTT 63 } vou_mix_prio; 64 65 typedef enum { 66 /* for video surface interface */ 67 VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_400 = 0x1, 68 VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_420 = 0x2, 69 VOU_LAYER_PIXERL_FORMAT_SP_YCBCR_422 = 0x3, 70 VOU_LAYER_PIXERL_FORMAT_BUTT 71 } vou_layer_pixerl_format; 72 73 typedef enum { 74 /* for device interface */ 75 VOU_INTF_PIXERL_FORMAT_YCBCR422 = 0x0, 76 VOU_INTF_PIXERL_FORMAT_YCBCR444 = 0xC, 77 VOU_INTF_PIXERL_FORMAT_RGB888 = 0xC, 78 VOU_INTF_PIXERL_FORMAT_BUTT 79 } vou_intf_pixerl_format; 80 81 typedef enum { 82 VO_CSC_DEF_VAL = 50, 83 VO_CSC_LUMA_MAX = 100, 84 VO_CSC_LUMA_MIN = 0, 85 86 VO_CSC_CONT_MAX = 100, 87 VO_CSC_CONT_MIN = 0, 88 89 VO_CSC_HUE_MAX = 100, 90 VO_CSC_HUE_MIN = 0, 91 92 VO_CSC_SAT_MAX = 100, 93 VO_CSC_SAT_MIN = 0, 94 } vo_csc_range; 95 96 /* vou zoom mode */ 97 typedef enum { 98 VOU_DISP_ZMEMODE_HORL = 0, 99 VOU_DISP_ZMEMODE_HORC, 100 VOU_DISP_ZMEMODE_VERL, 101 VOU_DISP_ZMEMODE_VERC, 102 103 VOU_DISP_ZMEMODE_HOR, 104 VOU_DISP_ZMEMODE_VER, 105 VOU_DISP_ZMEMODE_ALPHA, 106 VOU_DISP_ZMEMODE_ALPHAV, 107 VOU_DISP_ZMEMODE_VERT, 108 VOU_DISP_ZMEMODE_VERB, 109 110 VOU_DISP_ZMEMODE_ALL, 111 VOU_DISP_ZMEMODE_NONL, 112 VOU_DISP_ZMEMODE_BUTT 113 } vou_disp_zmemode; 114 115 typedef enum { 116 VO_HD_HW_DEV = 0, /* HD dev */ 117 VO_SD_HW_DEV, /* SD dev */ 118 VO_UHD_HW_DEV, /* UHD dev */ 119 VO_CAS_DEV, /* cascade dev */ 120 VO_VIRT_DEV, /* virtual dev */ 121 VO_DEV_TYPE_BUTT, 122 } vo_dev_type; 123 124 typedef struct { 125 vo_dev_type dev_type; /* dev type */ 126 hi_bool hd_vpss_rciv; /* */ 127 hi_bool sd_tde_disp; /* */ 128 hi_bool support_wbc; /* WBC support or not */ 129 hi_bool spt_get_screen_frm; /* */ 130 } vo_dev_capability; 131 132 typedef enum { 133 ICE_BIT_DEPTH_8 = 0, 134 ICE_BIT_DEPTH_10 = 1, 135 ICE_BIT_DEPTH_12 = 2, 136 ICE_BIT_DEPTH_14 = 3, 137 ICE_BIT_DEPTH_BUTT 138 } ice_bit_depth; 139 140 typedef enum { 141 ICE_REG_CFG_MODE_TYP = 0, 142 ICE_REG_CFG_MODE_MIN = 1, 143 ICE_REG_CFG_MODE_MAX = 2, 144 ICE_REG_CFG_MODE_RAND = 3, 145 ICE_REG_CFG_MODE_MINMAX = 4, 146 ICE_REG_CFG_MODE_MANUAL = 5, 147 ICE_REG_CFG_MODE_BUTT 148 } ice_reg_cfg_mode; 149 150 typedef enum { 151 ICE_DATA_FMT_YUV420 = 1, 152 ICE_DATA_FMT_YUV422 = 2, 153 ICE_DATA_FMT_BAYER = 3, 154 ICE_DATA_FMT_BUTT 155 } ice_data_fmt; 156 157 typedef enum { 158 ICE_BAYER_FMT_GRBG = 0, 159 ICE_BAYER_FMT_GBRG = 1, 160 ICE_BAYER_FMT_RGGB = 2, 161 ICE_BAYER_FMT_BGGR = 3, 162 ICE_BAYER_FMT_BUTT 163 } ice_bayer_fmt; 164 165 typedef struct { 166 /* input */ 167 hi_u32 layer; 168 hi_u32 frame_wth; 169 hi_u32 frame_hgt; 170 hi_u32 tile_hgt; 171 hi_u32 cmp_ratio; 172 hi_bool is_lossy; 173 hi_bool chm_proc_en; 174 hi_bool esl_en; 175 ice_bit_depth bit_depth; 176 ice_data_fmt data_fmt; 177 ice_bayer_fmt bayer_fmt; 178 ice_reg_cfg_mode cmp_cfg_mode; 179 /* file name */ 180 char **cmp_file_name; 181 /* output */ 182 hi_u32 *cmp_size; 183 /* debug */ 184 hi_u32 sti_err_type; 185 } cmp_seg_info; 186 187 typedef enum { 188 OSD_CMP_MODE_TYP = 0, 189 OSD_CMP_MODE_RAND, 190 OSD_CMP_MODE_BUTT 191 } osd_cmp_mode; 192 193 typedef struct { 194 /* input */ 195 hi_u32 layer; 196 osd_cmp_mode cmp_cfg_mode; 197 hi_u32 cmp_ratio; 198 /* file name */ 199 char **cmp_file_name; 200 /* output */ 201 hi_u32 *cmp_size; 202 /* debug */ 203 hi_u32 sti_err_type; 204 } cmp_frm_info; 205 206 typedef struct { 207 hi_u64 lum_addr; 208 hi_u64 chm_addr; 209 hi_u32 lum_str; 210 hi_u32 chm_str; 211 } vdp_cap_addr_info; 212 213 typedef enum { 214 VDP_CAP_ADDR_DATA = 0, /* 2d left eye data */ 215 VDP_CAP_ADDR_HEAD, /* dcmp head data */ 216 VDP_CAP_ADDR_3D, /* 3d right eye data */ 217 VDP_CAP_ADDR_BUTT 218 } vdp_cap_addr; 219 220 typedef enum { 221 VDP_CAP_INT_MODE_FRAME = 0, 222 VDP_CAP_INT_MODE_FIELD, 223 VDP_CAP_INT_BUTT 224 } vdp_cap_int_mode; 225 226 typedef struct { 227 hi_bool cmp_en; 228 hi_u32 cmp_ratio; 229 hi_bool is_lossy; 230 hi_bool esl_en; 231 ice_bit_depth bit_depth; 232 ice_data_fmt data_fmt; 233 ice_reg_cfg_mode cmp_cfg_mode; 234 235 hi_u32 lum_cmp_ratio; 236 hi_u32 chm_cmp_ratio; 237 hi_bool is_lum_lossy; 238 hi_bool is_chm_lossy; 239 hi_bool is_esl_mode; 240 hi_bool is_raw_mode; 241 } cmp_seg_cfg; 242 243 typedef struct { 244 /* src info */ 245 vdp_cap_addr_info addr[VDP_CAP_ADDR_BUTT]; 246 vdp_data_wth data_width; 247 vdp_proc_fmt data_fmt; 248 vdp_rect src_rect; 249 hi_u32 finfo; 250 /* bus */ 251 vdp_req_length req_len; 252 hi_u32 interval; 253 /* operation */ 254 cmp_seg_cfg seg_cfg; 255 /* operation */ 256 hi_bool flip_en; /* reserved */ 257 hi_bool uv_order; /* reserved */ 258 /* mmu */ 259 hi_bool smmu_en; /* reserved */ 260 } vdp_cap_cfg; 261 262 typedef struct { 263 /* basic cfg parameter */ 264 hi_s32 frm_hgt; 265 hi_s32 frm_wth; 266 hi_s32 bit_depth; /* 8,10,12,14 */ 267 hi_s32 lossy; 268 hi_s32 format; /* 1:420 2:422 3:bayer */ 269 hi_s32 bayer_format; /* RANGE:0-2 TYPICAL 0:GRBG 1:GBRG 2:RGGB 3:BGGR */ 270 hi_s32 esl_en; 271 hi_s32 esl_mode_qp; 272 hi_s32 cmp_ratio_pct_y; 273 hi_s32 type; /* */ 274 hi_s32 til_hgt; 275 hi_s32 c_en; 276 /* when type == 5, modifiable cfg parameter */ 277 hi_s32 line_buf_ref_sel; 278 hi_s32 dither_qp; 279 hi_s32 tol_num_y; 280 hi_s32 grad_ave_thr0_y; 281 hi_s32 grad_ave_thr1_y; 282 hi_s32 grad_ave_thr2_y; 283 hi_s32 simi_fct_thr0_y; 284 hi_s32 simi_fct_thr1_y; 285 hi_s32 simi_fct_thr2_y; 286 hi_s32 mb_offset_thr_y; 287 hi_s32 mb_offset_enable_y; 288 hi_s32 rc_qp_offset_y; 289 hi_s32 bgn_k_y; 290 hi_s32 max_k_y; 291 hi_s32 adp_k_y; 292 hi_s32 escape_intreim_y; 293 hi_s32 intreim_table_y; 294 hi_s32 round_y; 295 hi_s32 max_qp_offset_y; 296 hi_s32 dither_segots_y; 297 hi_s32 dither_ots_y; 298 hi_s32 dither_glb_y; 299 hi_s32 dither_dts_y; 300 hi_s32 dither_msq_y; 301 302 hi_s32 is_enc; 303 304 hi_s32 frm_num; 305 hi_s32 start_frm_num; 306 hi_s32 seg_wth; 307 hi_s32 mb_wth; 308 hi_s32 seg_ratio_maxpct; 309 hi_s32 tile_input; 310 hi_s32 mb_mode_sel_grad_thr; 311 hi_s32 seg_bst_align; 312 313 hi_s32 factor; 314 hi_s32 mb_independent; 315 hi_s32 raw_wdr_test; 316 hi_s32 pred_1ppc; 317 318 hi_s32 cmp_ratio_pct; 319 320 hi_s32 err_en; 321 } para_input; 322 323 typedef struct file vo_file; 324 325 typedef struct { 326 int frm_start; 327 int frm_len; 328 329 int frame_width; 330 int frame_height; 331 int bitdepth; 332 int cmp_mode; /* 0 --compress 1-- bypass raw */ 333 int is_lossless; 334 int comp_ratio_int; /* *1000 */ 335 int pixel_format; /* 1:420 2:422 3:bayer */ 336 int chroma_en; 337 int tile_en; 338 int tile_height; 339 int mirror_en; 340 int err_en; 341 int type; 342 /* when type == 5, modifiable cfg parameter */ 343 int grad_ave_thr0; 344 int grad_ave_thr1; 345 int grad_ave_thr2; 346 int simi_fct_thr0; 347 int simi_fct_thr1; 348 int simi_fct_thr2; 349 int rc_qp_offset; 350 int fix_k; 351 int max_qp_offset; 352 int seg_ratio_maxpct; 353 int mb_mode_sel_grad_thr; 354 int dither_qp; 355 int dither_segots; 356 int dither_ots; 357 int dither_glb; 358 int dither_dts; 359 int dither_msq; 360 } ice_v2r1_seg_256x1_para_input; 361 362 typedef struct { 363 hi_u32 fbdiv; 364 hi_u32 frac; 365 hi_u32 refdiv; 366 hi_u32 postdiv1; 367 hi_u32 postdiv2; 368 hi_u32 hdmiclk_div; 369 } vo_intfsync_pll; 370 371 typedef struct { 372 hi_u32 mirror_en; 373 hi_u16 cmp_mode; 374 hi_u16 frame_width; 375 hi_u16 frame_height; 376 hi_u16 chroma_en; 377 hi_u16 bitdepth; 378 hi_u16 tile_en; 379 hi_u16 tile_height; 380 hi_u16 is_lossless; 381 hi_u32 slc_cfg_tar_bit; 382 hi_u32 seg_cfg_max_bit; 383 hi_u32 seg_cfg_tar_bit; 384 hi_u32 max_qp; 385 386 hi_u16 dither_qp; 387 hi_u16 dither_segots; 388 hi_u16 dither_ots; 389 hi_u16 dither_glb; 390 hi_u16 dither_dts; 391 hi_u16 dither_msq; 392 393 /* tmu */ 394 hi_u16 grad_ave_thr0; 395 hi_u16 grad_ave_thr1; 396 hi_u16 grad_ave_thr2; 397 hi_u16 simi_fct_thr0; 398 hi_u16 simi_fct_thr1; 399 hi_u16 simi_fct_thr2; 400 hi_u16 rc_qp_offset; 401 hi_u16 fix_k; 402 hi_u16 mb_mode_sel_grad_thr; 403 404 vo_file *error; 405 hi_u32 err_en; 406 hi_u32 cmp_ratio; 407 } ice_v2r1_seg_256x1_rm_cfg; 408 409 /* ICE definition */ 410 typedef enum { 411 ICE_ERROR_TYPE_NORMAL = 0, 412 ICE_ERROR_TYPE_HEAD_ZERO, 413 ICE_ERROR_TYPE_HEAD_RAND, 414 ICE_ERROR_TYPE_HEAD_MAX, 415 ICE_ERROR_TYPE_DATA_ZERO, 416 ICE_ERROR_TYPE_DATA_RAND, 417 ICE_ERROR_TYPE_DATA_MAX, 418 ICE_ERROR_TYPE_FRAMESIZE_MAX, 419 ICE_ERROR_TYPE_FRAMESIZE_RAND, 420 ICE_ERROR_TYPE_FRAMESIZE_ZERO, 421 ICE_ERROR_TYPE_BUTT 422 } ice_error_type; 423 424 typedef struct { 425 hi_u32 layer; 426 hi_u32 frame_wth; 427 hi_u32 frame_hgt; 428 hi_u32 tile_hgt; 429 hi_u32 cmp_ratio_y; 430 hi_u32 cmp_ratio_c; 431 hi_bool cmp_en; 432 hi_bool is_raw_en; 433 hi_bool is_lossy_y; 434 hi_bool is_lossy_c; 435 hi_bool chm_proc_en; 436 hi_bool esl_en; 437 hi_bool csc_en; 438 ice_bit_depth bit_depth; 439 ice_data_fmt data_fmt; 440 ice_reg_cfg_mode cmp_cfg_mode; 441 /* file name */ 442 char *cmp_info; 443 char **cmp_file_name; 444 /* output */ 445 hi_u32 *cmp_size; 446 /* debug */ 447 ice_error_type err_type; 448 } ice_seg_cfg; 449 450 typedef struct { 451 /* vid layer */ 452 hi_u64 vid_lum_data_addr[VID_MAX]; 453 hi_u64 vid_chm_data_addr[VID_MAX]; 454 hi_u64 vid_lum_head_addr[VID_MAX]; 455 hi_u64 vid_chm_head_addr[VID_MAX]; 456 hi_u64 vid_lum2_bit_addr[VID_MAX]; 457 hi_u64 vid_chm2_bit_addr[VID_MAX]; 458 hi_u64 vid_lum_tile_addr[VID_MAX]; 459 hi_u64 vid_chm_tile_addr[VID_MAX]; 460 hi_u32 vid_lum_data_str[VID_MAX]; 461 hi_u32 vid_chm_data_str[VID_MAX]; 462 hi_u32 vid_lum_head_str[VID_MAX]; 463 hi_u32 vid_chm_head_str[VID_MAX]; 464 hi_u32 vid_lum2_bit_str[VID_MAX]; 465 hi_u32 vid_chm2_bit_str[VID_MAX]; 466 hi_u32 vid_lum_tile_str[VID_MAX]; 467 hi_u32 vid_chm_tile_str[VID_MAX]; 468 /* gfx layer */ 469 hi_u64 gfx_data_addr[GFX_MAX]; 470 hi_u64 gfx_dcmp_addr[GFX_MAX]; 471 hi_u32 gfx_data_str[GFX_MAX]; 472 hi_u32 gfx_dcmp_str[GFX_MAX]; 473 /* wbc layer */ 474 hi_u64 wbc_lum_data_addr[WBC_MAX]; 475 hi_u64 wbc_chm_data_addr[WBC_MAX]; 476 hi_u64 wbc_lum_head_addr[WBC_MAX]; 477 hi_u64 wbc_chm_head_addr[WBC_MAX]; 478 hi_u32 wbc_lum_data_str[WBC_MAX]; 479 hi_u32 wbc_chm_data_str[WBC_MAX]; 480 hi_u32 wbc_lum_head_str[WBC_MAX]; 481 hi_u32 wbc_chm_head_str[WBC_MAX]; 482 /* para */ 483 hi_u64 para_addr[PARA_MAX]; 484 } vo_addr_cfg; 485 486 typedef enum { 487 VDP_FDR_CFG_MODE_TYP, 488 VDP_FDR_CFG_MODE_TYP1, 489 VDP_FDR_CFG_MODE_RAND, 490 491 VDP_FDR_CFG_MODE_BUTT 492 } vdp_fdr_cfg_mode; 493 494 typedef struct { 495 hi_u64 lum_addr; 496 hi_u64 chm_addr; 497 498 hi_u32 lum_str; 499 hi_u32 chm_str; 500 } vdp_vid_addr_info; 501 502 typedef enum { 503 VDP_VID_ADDR_DATA = 0, /* 2d left eye data */ 504 VDP_VID_ADDR_2B, /* 2bit */ 505 VDP_VID_ADDR_HEAD, /* dcmp head data */ 506 VDP_VID_ADDR_3D, /* 3d right eye data */ 507 VDP_VID_ADDR_TILE_8B, /* tile 8bit */ 508 VDP_VID_ADDR_BUTT 509 } vdp_vid_addr; 510 511 typedef struct { 512 hi_u64 addr; 513 hi_u32 str; 514 } vdp_gfx_addr_info; 515 516 typedef enum { 517 VDP_GFX_ADDR_DATA = 0, /* 2d left eye data */ 518 VDP_GFX_ADDR_3D, /* 3d right eye data */ 519 VDP_GFX_ADDR_DCMP, /* dcmp head data */ 520 VDP_GFX_ADDR_DCMP_3D, /* dcmp head data */ 521 VDP_GFX_ADDR_BUTT 522 } vdp_gfx_addr; 523 524 typedef enum { 525 VDP_TESTPTTN_CLR_MODE_FIX = 0, 526 VDP_TESTPTTN_CLR_MODE_NORM, 527 VDP_TESTPTTN_CLR_MODE_BUTT 528 } vdp_testpttn_clr_mode; 529 530 typedef enum { 531 VDP_DCMP_SRC_MODE_ARGB8888 = 0, 532 VDP_DCMP_SRC_MODE_ARGB1555, 533 VDP_DCMP_SRC_MODE_ARGB4444, 534 VDP_DCMP_SRC_MODE_RGB565, 535 VDP_DCMP_SRC_MODE_RGB888, 536 VDP_DCMP_SRC_MODE_YUV444, 537 VDP_DCMP_SRC_MODE_BUTT 538 } vdp_dcmp_src_mode; 539 540 typedef enum { 541 VDP_CMP_MODE_CMP = 0, 542 VDP_CMP_MODE_RAW, 543 VDP_CMP_MODE_BUTT 544 } vdp_cmp_mode; 545 546 typedef enum { 547 VDP_TESTPTTN_LINEW_1P = 0, 548 VDP_TESTPTTN_LINEW_2P, 549 VDP_TESTPTTN_LINEW_BUTT 550 } vdp_testpttn_linew; 551 552 typedef struct { 553 hi_bool dcmp_en; 554 hi_bool is_esl_mode; 555 hi_bool is_raw_mode; 556 hi_bool is_lum_lossy; 557 hi_bool is_chm_lossy; 558 ice_reg_cfg_mode lum_cmp_mode; 559 ice_reg_cfg_mode chm_cmp_mode; 560 hi_u32 lum_cmp_ratio; /* reserved */ 561 hi_u32 chm_cmp_ratio; /* reserved */ 562 } vdp_dcmp_seg_cfg; 563 564 typedef struct { 565 hi_u64 addr; 566 hi_u32 str; 567 } vdp_addr; 568 569 #define MAX_REGION_NUM 64 570 #define V0_REGION_NUM 64 571 #define V1_REGION_NUM 16 572 #define V2_REGION_NUM 0 573 /* one region has 0x30 bytes(0x12000 ~ 0x12028), one region has 16( = 0x30 / 4) registers */ 574 #define REGION_OFFSET (0x30 / 4) 575 576 typedef enum { 577 VDP_REGION_ADDR_DATA_LUM = 0, 578 VDP_REGION_ADDR_DATA_CHM, 579 VDP_REGION_ADDR_HEAD_LUM, 580 VDP_REGION_ADDR_HEAD_CHM, 581 VDP_REGION_ADDR_BUTT 582 } vdp_region_addr; 583 584 typedef enum { 585 VDP_REGION_COLOR_MODE_FORE = 0, 586 VDP_REGION_COLOR_MODE_BACK, 587 VDP_REGION_COLOR_MODE_BUTT 588 } vdp_region_edge_color_mode; 589 590 typedef enum { 591 VDP_REGION_MUTE_MODE_SHOW = 0, 592 VDP_REGION_MUTE_MODE_NOSHOW, 593 VDP_REGION_MUTE_MODE_BUTT 594 } vdp_region_mute_mode; 595 596 typedef struct { 597 hi_bool region_en; 598 hi_bool mute_en; 599 hi_bool mmu_bypass; 600 hi_bool crop_en; 601 hi_bool edge_en; 602 hi_bool dcmp_en; 603 vdp_region_edge_color_mode edge_color_type; 604 vdp_rect disp_reso; 605 vdp_rect src_reso; 606 vdp_rect in_reso; 607 vdp_addr addr[VDP_REGION_ADDR_BUTT]; 608 } vdp_region_info; 609 610 typedef struct { 611 hi_u32 bkg_y; 612 hi_u32 bkg_u; 613 hi_u32 bkg_v; 614 615 hi_u32 bkg_a; 616 617 hi_u32 bk_type; 618 } vo_drv_bkg; 619 620 typedef struct { 621 hi_bool multi_region_en; 622 vdp_region_mute_mode multi_region_mute_mode; 623 hi_u32 region_num; 624 vdp_region_info region_info[MAX_REGION_NUM]; 625 } vdp_vid_fdr_mrg_cfg; 626 627 typedef struct { 628 /* src info */ 629 vdp_vid_addr_info addr[VDP_VID_ADDR_BUTT]; 630 631 vdp_vid_ifmt in_fmt; 632 vdp_data_wth data_width; 633 634 vdp_rect src_rect; 635 vdp_rect in_rect; 636 637 hi_bool smmu_en; /* reserved */ 638 639 vdp_data_rmode read_mode; /* lm & chm */ 640 hi_bool chm_copy_en; /* reserved */ 641 642 /* dcmp */ 643 vdp_dcmp_seg_cfg dcmp_cfg; 644 645 /* operation */ 646 hi_bool crop_en; 647 hi_bool flip_en; 648 hi_bool uv_order; 649 650 /* fdr mute */ 651 hi_bool fdr_mute_en; 652 hi_bool fdr_mute_req_en; 653 654 vo_drv_bkg fdr_mute_bkg; /* R,G,B */ 655 656 /* mac */ 657 hi_bool pre_rd_en; 658 hi_bool ofl_master; /* reserved */ 659 vdp_req_length req_len; 660 661 vdp_vid_fdr_mrg_cfg *mrg_cfg; 662 663 /* memory */ 664 hi_bool is_single_port; 665 hi_bool mem_mode; 666 } vdp_vid_fdr_cfg; 667 668 typedef struct { 669 hi_bool dcmp_en; 670 vdp_dcmp_src_mode dcmp_src_mode; 671 vdp_cmp_mode argb_cmp_mode; 672 hi_bool cmp_lostless; 673 hi_bool cmp_lostless_a; 674 675 hi_u32 dcmp_frame_size0; 676 hi_u32 dcmp_frame_size1; 677 } vdp_osd_dcmp_cfg; 678 679 typedef struct { 680 /* src info */ 681 vdp_gfx_addr_info addr[VDP_GFX_ADDR_BUTT]; 682 683 vdp_gfx_ifmt in_fmt; 684 685 vdp_rect src_rect; 686 687 hi_bool pre_mult_en; 688 689 /* palpha */ 690 hi_bool palpha_en; 691 hi_bool palpha_range_is_full; /* 0: 0~128, 1: 0~255 */ 692 693 /* for 1555 */ 694 hi_u32 alpha0; 695 hi_u32 alpha1; 696 697 /* read way */ 698 699 hi_bool flip_en; 700 701 /* pixel value calc */ 702 hi_bool ckey_en; 703 704 /* fdr mute */ 705 hi_bool fdr_mute_en; 706 hi_bool fdr_mute_req_en; 707 708 /* dcmp */ 709 vdp_osd_dcmp_cfg dcmp_cfg; 710 711 /* mac */ 712 hi_bool ofl_master; 713 vdp_req_length req_len; 714 715 /* mmu */ 716 hi_bool smmu_bypass_en; 717 718 /* memory */ 719 hi_bool port_mode; 720 721 /* axi */ 722 hi_bool latency_clr; 723 } vdp_gfx_fdr_cfg; 724 725 #define VO_ALL_COEF_SIZE 2000000 726 #define VO_COEF_OVER_SIZE 128 727 #define COEF_SIZE_V0_HZME (4096 * 128 / 8) 728 #define COEF_SIZE_V0_VZME (4096 * 128 / 8) 729 #define COEF_SIZE_V0_HDRD (4096 * 128 / 8) 730 #define COEF_SIZE_V0_HDRS (4096 * 128 / 8) 731 #define COEF_SIZE_G0_HDR_TMAP (4096 * 128 / 8) 732 #define COEF_SIZE_G0_HDR_GMM (4096 * 128 / 8) 733 #define COEF_SIZE_G0ZME (4096 * 128 / 8) 734 #define COEF_SIZE_WD_HZME (4096 * 128 / 8) 735 #define COEF_SIZE_WD_VZME (4096 * 128 / 8) 736 #define COEF_SIZE_WD_HDRD (4096 * 128 / 8) 737 #define COEF_SIZE_WD_HDRS (4096 * 128 / 8) 738 #define COEF_SIZE_REGION_V0 (192 * 128 / 8) 739 #define COEF_SIZE_REGION_V1 (48 * 128 / 8) 740 741 #define COEF_SIZE_SHARPEN (4096 * 128 / 8) /* (30 * 128/8 + VO_COEF_OVER_SIZE) */ 742 #define COEF_SIZE_DCI (4096 * 128 / 8) /* (35 * 128/8 + VO_COEF_OVER_SIZE) */ 743 #define COEF_SIZE_ACM (4096 * 128 / 8) /* (884 * 128/8 + VO_COEF_OVER_SIZE) */ 744 #define COEF_SIZE_VZME (4096 * 128 / 8) /* (33 * 128/8 + VO_COEF_OVER_SIZE) */ 745 #define COEF_SIZE_HZME (4096 * 128 / 8) /* (33 * 128/8 + VO_COEF_OVER_SIZE) */ 746 #define COEF_SIZE_GPZME (4096 * 128 / 8) /* (67 * 128/8 + VO_COEF_OVER_SIZE) */ 747 #define COEF_SIZE_DIM (4096 * 128 / 8) /* (127 * 128/8 + VO_COEF_OVER_SIZE) */ 748 #define COEF_SIZE_GMM (4096 * 128 / 8) /* (98 * 128/8 + VO_COEF_OVER_SIZE) */ 749 #define COEF_SIZE_OD (4096 * 128 / 8) /* (206 * 128/8 + VO_COEF_OVER_SIZE) */ 750 #define COEF_SIZE_CLUT (4096 * 128 / 8) /* (63 * 128/8 + VO_COEF_OVER_SIZE) */ 751 #define COEF_SIZE_PCID (4096 * 128 / 8) /* (37 * 128/8 + VO_COEF_OVER_SIZE) */ 752 #define COEF_SIZE_V0_ZME (4096 * 128 / 8) /* (37 * 128/8 + VO_COEF_OVER_SIZE) */ 753 754 /* video buf size: stride*h*2(flip)*2(3d) = (4096*10/8)*2160*2*2 ~= 0x3000000 */ 755 #define VO_BUF_SIZE_V0 0x3000000 756 #define VO_BUF_SIZE_V1 0x3000000 757 #define VO_BUF_SIZE_V2 0x3000000 758 #define VO_BUF_SIZE_V3 0x3000000 759 #define VO_BUF_SIZE_V4 0x3000000 760 761 typedef struct file vo_file; 762 763 typedef enum { 764 STI_FILE_DATA_VID0 = 0, 765 STI_FILE_DATA_VID1, 766 STI_FILE_DATA_VID2, 767 STI_FILE_DATA_VID3, 768 STI_FILE_DATA_VID4, 769 STI_FILE_DATA_GFX0, 770 STI_FILE_DATA_GFX1, 771 STI_FILE_DATA_GFX2, 772 STI_FILE_DATA_GFX3, 773 STI_FILE_DATA_GFX4, 774 775 STI_FILE_COEF_SR, 776 STI_FILE_COEF_ZME_V0, 777 STI_FILE_COEF_SHARPEN, 778 STI_FILE_COEF_ACM, 779 STI_FILE_COEF_DCI, 780 STI_FILE_COEF_DIM, 781 STI_FILE_COEF_GMM, 782 STI_FILE_COEF_CLUT, 783 STI_FILE_COEF_HZME, 784 STI_FILE_COEF_VZME, 785 STI_FILE_COEF_GPZME, 786 STI_FILE_COEF_OD, 787 STI_FILE_COEF_PCID, 788 STI_FILE_COEF_RGBW, 789 STI_FILE_COEF_DEMURA, 790 STI_FILE_TYPE_NODEF, 791 STI_FILE_V0_Y, 792 STI_FILE_V0_C, 793 STI_FILE_TILE_64_CMP_Y, 794 STI_FILE_TILE_64_CMP_C, 795 STI_FILE_TILE_64_CMP_Y_2BIT, 796 STI_FILE_TILE_64_CMP_C_2BIT, 797 STI_FILE_TILE_64_CMP_Y_HEAD, 798 STI_FILE_TILE_64_CMP_C_HEAD, 799 STI_FILE_OSD_CMP, 800 STI_FILE_COEF_DM, 801 STI_FILE_COEF_GDM, 802 STI_FILE_COEF_METADATA, 803 STI_FILE_DATA_TNR_REF, 804 STI_FILE_DATA_TNR_MAD, 805 STI_FILE_DATA_TNR_RGMV, 806 STI_FILE_TNR_REF_CMP_Y, 807 STI_FILE_COEF_TONEMAP, 808 809 STI_FILE_DATA_VMX, 810 STI_FILE_COEF_HIHDR_V_D, 811 STI_FILE_COEF_HIHDR_V, 812 STI_FILE_COEF_HIHDR_G_TMAP, 813 STI_FILE_COEF_HIHDR_G_GMM, 814 STI_FILE_COEF_G0ZME, 815 STI_FILE_COEF_WD_HZME, 816 STI_FILE_COEF_WD_VZME, 817 STI_FILE_COEF_HIHDR_WD_D, 818 STI_FILE_COEF_HIHDR_WD, 819 820 STI_FILE_TYPE_BUTT 821 } sti_file_type; 822 823 typedef struct { 824 hi_u32 data3; 825 hi_u32 data2; 826 hi_u32 data1; 827 hi_u32 data0; 828 hi_u32 depth; 829 } vo_drv_u128; 830 831 typedef enum { 832 DRV_COEF_DATA_TYPE_U8 = 0, 833 DRV_COEF_DATA_TYPE_S8, 834 DRV_COEF_DATA_TYPE_U16, 835 DRV_COEF_DATA_TYPE_S16, 836 DRV_COEF_DATA_TYPE_U32, 837 DRV_COEF_DATA_TYPE_S32, 838 DRV_COEF_DATA_TYPE_BUTT 839 } vo_drv_coef_data_type; 840 841 typedef struct { 842 hi_u8 *coef_addr; 843 sti_file_type sti_type; 844 vo_file *fp_coef; 845 hi_u32 lut_num; 846 hi_u32 burst_num; 847 hi_u32 cycle_num; 848 void **coef_array; 849 hi_u32 *lut_length; 850 hi_u32 *coef_bit_length; 851 vo_drv_coef_data_type data_type; 852 } vo_drv_coef_send_cfg; 853 854 typedef enum { 855 VO_RM_COEF_MODE_TYP = 0x0, 856 VO_RM_COEF_MODE_RAN = 0x1, 857 VO_RM_COEF_MODE_MIN = 0x2, 858 VO_RM_COEF_MODE_MAX = 0x3, 859 VO_RM_COEF_MODE_ZRO = 0x4, 860 VO_RM_COEF_MODE_CUS = 0x5, 861 VO_RM_COEF_MODE_UP = 0x6, 862 VO_RM_COEF_MODE_BUTT 863 } vo_rm_coef_mode; 864 865 typedef struct { 866 hi_u64 start_phy_addr; 867 hi_void *start_vir_addr; 868 hi_u32 size; 869 } vo_mmz_buffer; 870 871 typedef enum { 872 VO_BUF_V0 = 0, 873 VO_BUF_V1, 874 VO_BUF_V2, 875 VO_BUF_V3, 876 VO_BUF_V4, 877 VO_BUF_G0, 878 VO_BUF_G1, 879 VO_BUF_G2, 880 VO_BUF_G3, 881 VO_BUF_G4, 882 VO_BUF_G5, 883 VO_BUF_BUTT 884 } vo_layer_buf; 885 886 typedef enum { 887 VO_COEF_BUF_V0_HZME = 0, 888 VO_COEF_BUF_V0_VZME = 1, 889 VO_COEF_BUF_V0_HDRD = 2, 890 VO_COEF_BUF_V0_HDRS = 3, 891 VO_COEF_BUF_G0_HDR_TMAP = 4, 892 VO_COEF_BUF_G0_HDR_GMM = 5, 893 VO_COEF_BUF_G0ZME = 6, 894 VO_COEF_BUF_WD_HZME = 7, 895 VO_COEF_BUF_WD_VZME = 8, 896 VO_COEF_BUF_WD_HDRD = 9, 897 VO_COEF_BUF_WD_HDRS = 10, 898 899 VO_COEF_BUF_REGION_V0 = 12, 900 VO_COEF_BUF_REGION_V1 = 13, 901 VO_COEF_BUF_SHARPEN, 902 VO_COEF_BUF_DCI, 903 VO_COEF_BUF_ACM, 904 VO_COEF_BUF_VZME, 905 VO_COEF_BUF_HZME, 906 VO_COEF_BUF_GPZME, 907 VO_COEF_BUF_DIM, 908 VO_COEF_BUF_GMM, 909 VO_COEF_BUF_OD, 910 VO_COEF_BUF_CLUT, 911 VO_COEF_BUF_PCID, 912 913 VO_COEF_BUF_ALL = 32, 914 VO_COEF_BUF_BUTT = 33 915 } vo_coef_buf; 916 917 typedef struct { 918 vo_mmz_buffer buf_base_addr; 919 hi_u32 u32size; 920 921 hi_u8 *coef_vir_addr[VO_COEF_BUF_BUTT]; 922 hi_u64 coef_phy_addr[VO_COEF_BUF_BUTT]; 923 } vo_coef_addr; 924 925 typedef struct { 926 vo_mmz_buffer buf_base_addr; 927 hi_u32 u32size; 928 929 hi_u32 buf_addr[VO_BUF_BUTT]; 930 } vo_layer_buf_addr; 931 932 typedef enum { 933 VO_HIHDR_V_TYP = 0, 934 VO_HIHDR_V_TYP1, 935 VO_HIHDR_V_RAND, 936 VO_HIHDR_V_MAX, 937 VO_HIHDR_V_MIN, 938 VO_HIHDR_V_ZERO, 939 VO_HIHDR_V_BUTT 940 } vo_hihdr_v_mode; 941 942 typedef enum { 943 VO_VHDR_GAMUT_TO_TONEMAP = 0, 944 VO_VHDR_TONEMAP_TO_GAMUT = 1 945 } vo_vhdr_gamut_bind; 946 947 typedef enum { 948 VO_VHDR_Y2R_BT709 = 0, 949 VO_VHDR_Y2R_BT2020 = 1, 950 VO_VHDR_Y2R_XVYCC = 2, 951 VO_VHDR_Y2R_BUTT 952 } vo_vhdr_y2r_cfg_mode; 953 954 typedef enum { 955 VO_CSC_V0_TYP = 0, 956 VO_CSC_V0_TYP1, 957 VO_CSC_V0_RAND, 958 VO_CSC_V0_MAX, 959 VO_CSC_V0_MIN, 960 VO_CSC_V0_ZERO, 961 VO_CSC_V0_BUTT 962 } vo_csc_v0_mode; 963 964 typedef enum { 965 VHDR_HDR10_IN_SDR_OUT = 0, 966 VHDR_HDR10_IN_HLG_OUT, 967 VHDR_HLG_IN_SDR_OUT, 968 VHDR_HLG_IN_HDR10_OUT, 969 VHDR_SDR10_IN_SDR8_OUT, 970 VHDR_XVYCC, 971 VHDR_SDR2020CL_IN_709_OUT, 972 VHDR_BUTT 973 } vhdr_scene_mode; 974 975 typedef struct { 976 /* module ctrl */ 977 hi_u32 vhdr_en; 978 hi_u32 vhdr_ck_gt_en; 979 hi_u32 vhdr_degmm_en; 980 hi_u32 vhdr_gamut_en; 981 hi_u32 vhdr_tmap_en; 982 hi_u32 vhdr_gmm_en; 983 hi_u32 vhdr_dither_en; 984 hi_u32 vhdr_r2y_en; 985 hi_u32 vhdr_cadj_en; 986 hi_u32 vhdr_gamut_bind; 987 988 /* dither ctrl */ 989 hi_u32 vhdr_dither_round_unlim; 990 hi_u32 vhdr_dither_round; 991 hi_u32 vhdr_dither_domain_mode; 992 hi_u32 vhdr_dither_tap_mode; 993 994 /* hi_hdr scene */ 995 vhdr_scene_mode scene_mode; 996 } vo_hihdr_v_cfg; 997 998 typedef struct { 999 /* module ctrl */ 1000 hi_u32 hihdr_y2r_en; 1001 hi_u32 hihdr_y2r_ck_gt_en; 1002 1003 /* PIP ctrl */ 1004 hi_u32 hihdr_v0_y2r_en; 1005 hi_u32 hihdr_v1_y2r_en; 1006 hi_u32 hihdr_v0_vhdr_en; 1007 hi_u32 hihdr_v1_vhdr_en; 1008 hi_u32 hihdr_v0_cl_en; 1009 hi_u32 hihdr_v1_cl_en; 1010 1011 /* demo ctrl */ 1012 hi_u32 hihdr_v_demo_en; 1013 hi_u32 hihdr_v_demo_mode; 1014 hi_u32 hihdr_v_demo_pos; 1015 1016 /* hi_hdr scene */ 1017 vhdr_scene_mode scene_mode; 1018 } vo_csc_v0_cfg; 1019 1020 typedef struct { 1021 hi_u32 ck_gt_en; 1022 hi_u32 hfir_order; 1023 hi_u32 lhfir_en; 1024 hi_u32 chfir_en; 1025 hi_u32 lhmid_en; 1026 hi_u32 chmid_en; 1027 hi_u32 non_lnr_en; 1028 hi_u32 lhfir_mode; 1029 hi_u32 chfir_mode; 1030 hi_u32 hl_shootctrl_en; 1031 hi_u32 hl_shootctrl_mode; 1032 hi_u32 hc_shootctrl_en; 1033 hi_u32 hc_shootctrl_mode; 1034 1035 hi_u32 in_pro; 1036 hi_u32 out_pro; 1037 hi_u32 out_fmt; 1038 hi_u64 in_height; 1039 hi_u64 out_height; 1040 hi_u64 in_width; 1041 hi_u64 out_width; 1042 hi_u32 graphdet_en; 1043 1044 hi_u32 lvfir_en; 1045 hi_u32 cvfir_en; 1046 hi_u32 lvmid_en; 1047 hi_u32 cvmid_en; 1048 hi_u32 vfir_1tap_en; 1049 hi_u32 lvfir_mode; 1050 hi_u32 cvfir_mode; 1051 hi_u32 vl_shootctrl_en; 1052 hi_u32 vl_shootctrl_mode; 1053 hi_u32 vc_shootctrl_en; 1054 hi_u32 vc_shootctrl_mode; 1055 } vo_v0_zme_cfg; 1056 1057 typedef struct { 1058 hi_u32 vluma_offset; 1059 hi_u32 vchroma_offset; 1060 hi_u32 vbluma_offset; 1061 hi_u32 vbchroma_offset; 1062 hi_u32 lhfir_offset; 1063 hi_u32 chfir_offset; 1064 hi_u32 vl_flatdect_mode; 1065 hi_u32 vl_coringadj_en; 1066 hi_u32 vl_gain; 1067 hi_u32 vl_coring; 1068 hi_u32 vc_flatdect_mode; 1069 hi_u32 vc_coringadj_en; 1070 hi_u32 vc_gain; 1071 hi_u32 vc_coring; 1072 hi_u32 hl_flatdect_mode; 1073 hi_u32 hl_coringadj_en; 1074 hi_u32 hl_gain; 1075 hi_u32 hl_coring; 1076 hi_u32 hc_flatdect_mode; 1077 hi_u32 hc_coringadj_en; 1078 hi_u32 hc_gain; 1079 hi_u32 hc_coring; 1080 } vo_zme_comm_pq_cfg; 1081 1082 typedef struct { 1083 hi_u32 zme_vprec; 1084 hi_u32 zme_hprec; 1085 } vo_zme_ds_info; 1086 1087 typedef enum { 1088 VO_ZME_TYP = 0, 1089 VO_ZME_TYP1, 1090 VO_ZME_RAND, 1091 VO_ZME_MAX, 1092 VO_ZME_MIN, 1093 VO_ZME_ZERO, 1094 VO_ZME_BUTT 1095 } vo_zme_mode; 1096 1097 typedef enum { 1098 XDP_ZME_HFIR_ORDER_HV = 0, 1099 XDP_ZME_HFIR_ORDER_VH, 1100 XDP_ZME_HFIR_ORDER_BUTT 1101 } xdp_zme_hfir_order; 1102 1103 typedef enum { 1104 VDP_V0_HFIR_TYP = 0, 1105 VDP_V0_HFIR_TYP1, 1106 VDP_V0_HFIR_RAND, 1107 VDP_V0_HFIR_MAX, 1108 VDP_V0_HFIR_MIN, 1109 VDP_V0_HFIR_ZERO, 1110 VDP_V0_HFIR_BUTT 1111 } vo_v0_hfir_mode; 1112 1113 typedef enum { 1114 XDP_V0_HFIR_BYPASS = 0, 1115 XDP_V0_HFIR_COPY, 1116 XDP_V0_HFIR_BILT, 1117 XDP_V0_HFIR_FILT, 1118 XDP_V0_HFIR_BUTT 1119 } xdp_v0_hfir_mode; 1120 1121 typedef struct { 1122 hi_u32 ck_gt_en; /* use for cfg ck_gt_en */ 1123 hi_u32 mid_en; 1124 xdp_v0_hfir_mode hfir_mode; /* use for cfg mode */ 1125 } vo_v0_hfir_cfg; 1126 1127 typedef struct { 1128 hi_u32 vid_iw; 1129 hi_u32 vid_ih; 1130 hi_u32 vid_ow; 1131 hi_u32 vid_oh; 1132 1133 hi_u32 zme_en; 1134 hi_u32 hfir_en; 1135 hi_u32 csc_en; 1136 hi_u32 hdr_en; 1137 1138 vo_v0_zme_cfg zme_cfg; 1139 vo_v0_hfir_cfg hfir_cfg; 1140 vo_csc_v0_cfg yuv2rgb_cfg; 1141 vo_hihdr_v_cfg v_hihdr_cfg; 1142 } vdp_vid_ip_cfg; 1143 1144 /* for V1 */ 1145 typedef struct { 1146 hi_u32 ck_gt_en; 1147 hi_u32 out_pro; 1148 hi_u32 out_fmt; 1149 hi_u64 in_height; 1150 hi_u64 out_height; 1151 hi_u64 in_width; 1152 hi_u64 out_width; 1153 hi_u32 cvfir_en; 1154 hi_u32 cvmid_en; 1155 hi_u32 cvfir_mode; 1156 1157 hi_u32 hfir_order; 1158 hi_u32 lhfir_en; 1159 hi_u32 chfir_en; 1160 hi_u32 lhmid_en; 1161 hi_u32 chmid_en; 1162 hi_u32 non_lnr_en; 1163 hi_u32 lhfir_mode; 1164 hi_u32 chfir_mode; 1165 hi_u32 hl_shootctrl_en; 1166 hi_u32 hl_shootctrl_mode; 1167 hi_u32 hc_shootctrl_en; 1168 hi_u32 hc_shootctrl_mode; 1169 1170 hi_u32 in_pro; 1171 hi_u32 graphdet_en; 1172 1173 hi_u32 lvfir_en; 1174 hi_u32 lvmid_en; 1175 hi_u32 vfir_1tap_en; 1176 hi_u32 lvfir_mode; 1177 hi_u32 vl_shootctrl_en; 1178 hi_u32 vl_shootctrl_mode; 1179 hi_u32 vc_shootctrl_en; 1180 hi_u32 vc_shootctrl_mode; 1181 } vdp_v1_cvfir_cfg; 1182 typedef enum { 1183 VDP_V1_HFIR_TYP = 0, 1184 VDP_V1_HFIR_TYP1, 1185 VDP_V1_HFIR_RAND, 1186 VDP_V1_HFIR_MAX, 1187 VDP_V1_HFIR_MIN, 1188 VDP_V1_HFIR_ZERO, 1189 VDP_V1_HFIR_BUTT 1190 } vdp_v1_hfir_mode; 1191 1192 typedef enum { 1193 XDP_HFIR_BYPASS = 0, 1194 XDP_HFIR_COPY, 1195 XDP_HFIR_BILT, 1196 XDP_HFIR_FILT, 1197 XDP_HFIR_BUTT 1198 } xdp_hfir_mode; 1199 1200 typedef struct { 1201 hi_u32 ck_gt_en; /* use for ck_gt_en */ 1202 hi_u32 mid_en; 1203 xdp_hfir_mode hfir_mode; /* use for mode */ 1204 } vdp_v1_hfir_cfg; 1205 1206 typedef struct { 1207 hi_u32 csc_en; 1208 hi_u32 csc_ck_gt_en; 1209 } vdp_csc_v1_cfg; 1210 1211 typedef enum { 1212 DITHER_IO_MODE_12_10 = 1, 1213 DITHER_IO_MODE_12_8 = 2, 1214 DITHER_IO_MODE_10_8 = 3, 1215 DITHER_IO_MODE_10_6 = 4, 1216 DITHER_IO_MODE_9_6 = 5, 1217 DITHER_IO_MODE_8_6 = 6, 1218 DITHER_IO_MODE_10_9_6 = 5, 1219 DITHER_IO_MODE_10_8_6 = 6, 1220 DITHER_IO_MODE_BUTT 1221 } dither_io_mode; 1222 1223 typedef struct { 1224 hi_u32 dither_en; 1225 hi_u32 dither_mode; 1226 hi_u32 dither_round; 1227 hi_u32 dither_round_unlim; 1228 hi_u32 i_data_width_dither; 1229 hi_u32 o_data_width_dither; 1230 hi_u32 dither_domain_mode; 1231 hi_u32 dither_tap_mode; 1232 hi_u32 dither_sed_y0; 1233 hi_u32 dither_sed_u0; 1234 hi_u32 dither_sed_v0; 1235 hi_u32 dither_sed_w0; 1236 hi_u32 dither_sed_y1; 1237 hi_u32 dither_sed_u1; 1238 hi_u32 dither_sed_v1; 1239 hi_u32 dither_sed_w1; 1240 hi_u32 dither_sed_y2; 1241 hi_u32 dither_sed_u2; 1242 hi_u32 dither_sed_v2; 1243 hi_u32 dither_sed_w2; 1244 hi_u32 dither_sed_y3; 1245 hi_u32 dither_sed_u3; 1246 hi_u32 dither_sed_v3; 1247 hi_u32 dither_sed_w3; 1248 hi_u32 dither_thr_max; 1249 hi_u32 dither_thr_min; 1250 dither_io_mode io_mode; 1251 } vdp_dither_cfg; 1252 1253 typedef enum { 1254 VDP_DITHER_MODE_TYP = 0, 1255 VDP_DITHER_MODE_TYP1, 1256 VDP_DITHER_MODE_RAND, 1257 VDP_DITHER_MODE_MAX, 1258 VDP_DITHER_MODE_MIN, 1259 VDP_DITHER_MODE_ZERO, 1260 VDP_DITHER_MODE_BUTT 1261 } vdp_dither_mode; 1262 1263 typedef enum { 1264 DITHER_MODE_10BIT = 0, 1265 DITHER_MODE_8BIT = 1, 1266 DITHER_MODE_BUTT 1267 } dither_mode; 1268 1269 typedef enum { 1270 DITHER_OWIDTH_MODE_5BIT = 0, 1271 DITHER_OWIDTH_MODE_6BIT = 1, 1272 DITHER_OWIDTH_MODE_7BIT = 2, 1273 DITHER_OWIDTH_MODE_8BIT = 3, 1274 DITHER_OWIDTH_MODE_9BIT = 4, 1275 DITHER_OWIDTH_MODE_10BIT = 5, 1276 DITHER_OWIDTH_MODE_BUTT 1277 } dither_owidth_mode; 1278 1279 typedef enum { 1280 DITHER_IWIDTH_MODE_8BIT = 0, 1281 DITHER_IWIDTH_MODE_9BIT = 1, 1282 DITHER_IWIDTH_MODE_10BIT = 2, 1283 DITHER_IWIDTH_MODE_11BIT = 3, 1284 DITHER_IWIDTH_MODE_12BIT = 4, 1285 DITHER_IWIDTH_MODE_BUTT 1286 } dither_iwidth_mode; 1287 1288 typedef enum { 1289 DITHER_DOMAIN_MODE_SPACE = 0, 1290 DITHER_DOMAIN_MODE_TIME = 1, 1291 DITHER_DOMAIN_MODE_BUTT 1292 } dither_domain_mode; 1293 1294 typedef enum { 1295 DITHER_TAP_MODE_7 = 0, 1296 DITHER_TAP_MODE_15 = 1, 1297 DITHER_TAP_MODE_23 = 2, 1298 DITHER_TAP_MODE_31 = 3, 1299 DITHER_TAP_MODE_BUTT 1300 } dither_tap_mode; 1301 1302 typedef struct { 1303 hi_u32 dither_in_bit_width; 1304 hi_u32 dither_out_bit_width; 1305 } vo_dither_info; 1306 1307 vo_coef_addr *vo_drv_get_coef_buf_addr(hi_void); 1308 hi_void vo_drv_v_set_v0_zme_coef(vo_rm_coef_mode coef_mode); 1309 1310 #define SEG_WIDTH 256 1311 1312 hi_bool vou_drv_is_virt_dev(hi_vo_dev dev); 1313 1314 hi_void vou_drv_set_dev_dither_mode(hi_vo_dev dev, vdp_dither_mode dither_mode_set, vdp_dither_cfg *cfg); 1315 1316 hi_void vou_drv_board_init(hi_void); 1317 hi_void vou_drv_board_de_init(hi_void); 1318 hi_void vo_drv_int_reg_up_mode(hi_vo_layer layer, vo_int_mode int_mode); 1319 hi_void vou_drv_set_dev_intf_type(hi_vo_dev dev, hi_vo_intf_type intf_type); 1320 hi_void vou_drv_set_dev_bk_grd(hi_vo_dev dev, hi_u32 bg_color); 1321 hi_void vou_drv_set_dev_out_sync(hi_vo_dev dev, hi_vo_intf_sync vo_out_mode); 1322 hi_void vou_drv_set_dev_default_vtth(hi_vo_dev dev); 1323 hi_s32 vou_drv_set_dev_vtth(hi_vo_dev dev, hi_u32 vtth); 1324 hi_void vou_drv_get_dev_vtth(hi_vo_dev dev, hi_u32 *vtth); 1325 hi_bool vou_drv_is_support_save_buf_mode(hi_void); 1326 hi_void vou_drv_set_dev_default_vtth2(hi_vo_dev dev); 1327 hi_s32 vou_drv_set_dev_vtth2(hi_vo_dev dev, hi_u32 vtth); 1328 hi_void vou_drv_get_dev_vtth2(hi_vo_dev dev, hi_u32 *vtth); 1329 hi_void vou_drv_set_dev_dither_out(hi_vo_dev dev, hi_u32 out_bit_width); 1330 hi_void vou_drv_set_dev_dither(hi_vo_dev dev, hi_u32 in); 1331 hi_bool vou_drv_get_dev_enable(hi_vo_dev dev); 1332 hi_s32 vou_drv_check_usr_sync_timing(hi_vo_dev dev, hi_vo_sync_info *cfg); 1333 hi_void vou_drv_set_usr_sync_timing(hi_vo_sync_info *cfg); 1334 hi_s32 vo_drv_check_dev_user_sync_info(hi_vo_dev dev, hi_vo_user_intfsync_info *user_info); 1335 hi_void vo_drv_set_dev_user_intf_sync_attr(hi_vo_dev dev, hi_vo_user_intfsync_attr *user_attr); 1336 hi_void vo_drv_set_dev_div(hi_vo_dev dev, hi_u32 dev_div); 1337 hi_void vo_drv_set_hdmi_div(hi_vo_dev dev, hi_u32 pre_div); 1338 hi_void vo_drv_set_clk_reverse(hi_bool reverse); 1339 1340 /* interrupt relative */ 1341 hi_void vo_drv_dev_int_enable(hi_vo_dev dev, hi_bool enable); 1342 hi_void vou_drv_int_clear(hi_u32 int_clear); 1343 hi_void vou_drv_int_disable_all(hi_void); 1344 hi_void vo_drv_int_set_mode(hi_vo_dev dev, vo_int_mode int_mode); 1345 1346 /* surface relative */ 1347 hi_void vou_drv_layer_enable(hi_vo_layer layer, hi_bool enable); 1348 hi_void vou_drv_set_layer_bk_grd(hi_vo_layer layer, hi_u32 bk_grd); 1349 hi_void vou_drv_set_layer_data_fmt(hi_vo_layer layer, vou_layer_pixerl_format data_fmt); 1350 hi_void vou_drv_get_layer_data_fmt(hi_vo_layer layer, vou_layer_pixerl_format *data_fmt); 1351 hi_void vou_drv_set_multi_area_enable(hi_vo_layer layer, 1352 hi_u32 u32area_num, 1353 hi_bool enable); 1354 hi_void vou_drv_set_multi_addr_stride(hi_vo_layer layer, 1355 hi_u32 area_num, 1356 hi_u32 layer_luma_addr, 1357 hi_u32 layer_chroma_addr, 1358 hi_u32 layer_luma_stride, 1359 hi_u32 layer_chroma_stride); 1360 1361 1362 hi_void vou_drv_layer_csc_enable(hi_vo_layer layer, hi_bool csc_en); 1363 1364 hi_void vou_drv_def_layer_bind_dev(hi_void); 1365 1366 hi_void vo_drv_set_dev_bg_color(hi_vo_dev dev, hi_u32 u32bgcolor, hi_bool rgb); 1367 hi_void vo_drv_open(hi_vo_dev dev); 1368 hi_void vo_drv_close(hi_vo_dev dev); 1369 hi_void vo_drv_enable(hi_vo_dev dev); 1370 hi_void vo_drv_disable(hi_vo_dev dev); 1371 1372 hi_void vo_drv_get_dev_hal_id(hi_vo_dev dev, vo_hal_dev *hi_vo_dev); 1373 hi_void vo_drv_get_channel_hal_id(hi_vo_dev dev, hal_disp_outputchannel *vo_channel); 1374 hi_void vou_drv_default_setting(hi_void); 1375 hi_void vo_drv_transparent_transmit_setting(hi_bool transparent_transmit); 1376 hi_s32 vou_drv_check_dev_id(hi_vo_dev dev); 1377 hi_void vo_drv_dev_info_init(hi_void); 1378 hi_void vo_drv_dev_info_part_init(hi_void); 1379 hi_void vo_drv_dev_info_de_init(hi_void); 1380 1381 hi_bool vo_drv_is_phy_dev_hd(hi_vo_dev dev); 1382 hi_bool vo_drv_is_phy_dev_sd(hi_vo_dev dev); 1383 hi_bool vou_drv_special_work_flow(hi_vo_dev dev); 1384 1385 hi_s32 vou_drv_set_dev_full_frame_rate(hi_vo_dev dev, hi_u32 frame_rate); 1386 hi_s32 vou_drv_check_dev_pub_attr(hi_vo_dev dev, hi_vo_pub_attr *pub_attr); 1387 hi_s32 vou_drv_set_pub_attr(hi_vo_dev dev, hi_vo_pub_attr *vo_pub_attr); 1388 hi_s32 vou_drv_set_user_sync_info(hi_vo_dev dev, hi_vo_user_intfsync_info *info); 1389 hi_void vou_drv_set_disp_max_size(hi_vo_dev dev, hi_u32 max_width, hi_u32 max_height); 1390 hi_s32 vou_drv_set_dev_clk(hi_vo_dev dev); 1391 1392 1393 hi_void vo_drv_set_all_crg_clk(hi_bool clk_en); 1394 hi_void vo_drv_set_hd_clk_sel(hi_u32 hd_clk_sel); 1395 hi_void vo_lpw_bus_reset(hi_bool reset); 1396 hi_void vo_set_low_power_ctrl_clk_en(hi_bool clk_en); 1397 hi_void vou_drv_init_default_csc(hi_vo_layer layer); 1398 1399 hi_void vou_drv_lbw_show_proc(osal_proc_entry_t *s); 1400 1401 #ifdef __cplusplus 1402 #if __cplusplus 1403 } 1404 #endif 1405 #endif /* end of #ifdef __cplusplus */ 1406 1407 #endif /* end of __VOU_DRV_H__ */ 1408