1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18 #include "hdmi_reg_video_path.h"
19 #include "hdmi_product_define.h"
20
21 volatile video_path_reg_regs_type *g_video_path_regs = NULL;
22
hdmi_reg_video_path_regs_init(hi_char * addr)23 int hdmi_reg_video_path_regs_init(hi_char *addr)
24 {
25 g_video_path_regs = (volatile video_path_reg_regs_type *)(addr + HDMI_TX_BASE_ADDR_VIDEO);
26 return HI_SUCCESS;
27 }
28
hdmi_reg_video_path_regs_deinit(void)29 int hdmi_reg_video_path_regs_deinit(void)
30 {
31 if (g_video_path_regs != HI_NULL) {
32 g_video_path_regs = HI_NULL;
33 }
34 return HI_SUCCESS;
35 }
36
hdmi_reg_sync_polarity_set(unsigned int reg_sync_polarity)37 int hdmi_reg_sync_polarity_set(unsigned int reg_sync_polarity)
38 {
39 hi_u32 *reg_addr = NULL;
40 timing_gen_ctrl gen_ctrl;
41
42 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
43 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
44 gen_ctrl.bits.reg_sync_polarity = reg_sync_polarity;
45 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32);
46
47 return HI_SUCCESS;
48 }
49
hdmi_reg_sync_polarity_get(hi_void)50 hi_u32 hdmi_reg_sync_polarity_get(hi_void)
51 {
52 hi_u32 *reg_addr = NULL;
53 timing_gen_ctrl gen_ctrl;
54
55 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
56 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
57 return gen_ctrl.bits.reg_sync_polarity;
58 }
59
hdmi_reg_timing_sel_set(unsigned int reg_timing_sel)60 int hdmi_reg_timing_sel_set(unsigned int reg_timing_sel)
61 {
62 hi_u32 *reg_addr = NULL;
63 timing_gen_ctrl gen_ctrl;
64
65 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
66 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
67 gen_ctrl.bits.reg_timing_sel = reg_timing_sel;
68 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32);
69
70 return HI_SUCCESS;
71 }
72
hdmi_reg_timing_sel_get(hi_void)73 hi_u32 hdmi_reg_timing_sel_get(hi_void)
74 {
75 hi_u32 *reg_addr = NULL;
76 timing_gen_ctrl gen_ctrl;
77
78 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
79 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
80 return gen_ctrl.bits.reg_timing_sel;
81 }
82
hdmi_reg_extmode_set(unsigned int reg_extmode)83 int hdmi_reg_extmode_set(unsigned int reg_extmode)
84 {
85 hi_u32 *reg_addr = NULL;
86
87 timing_gen_ctrl gen_ctrl;
88
89 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
90 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
91 gen_ctrl.bits.reg_extmode = reg_extmode;
92 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32);
93
94 return HI_SUCCESS;
95 }
96
hdmi_reg_extmode_get(hi_void)97 hi_u32 hdmi_reg_extmode_get(hi_void)
98 {
99 hi_u32 *reg_addr = NULL;
100 timing_gen_ctrl gen_ctrl;
101
102 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
103 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
104 return gen_ctrl.bits.reg_extmode;
105 }
106
hdmi_reg_timing_gen_en_set(unsigned int reg_timing_gen_en)107 int hdmi_reg_timing_gen_en_set(unsigned int reg_timing_gen_en)
108 {
109 hi_u32 *reg_addr = NULL;
110 timing_gen_ctrl gen_ctrl;
111
112 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
113 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
114 gen_ctrl.bits.reg_timing_gen_en = reg_timing_gen_en;
115 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32);
116
117 return HI_SUCCESS;
118 }
119
hdmi_reg_timing_gen_en_get(hi_void)120 hi_u32 hdmi_reg_timing_gen_en_get(hi_void)
121 {
122 hi_u32 *reg_addr = NULL;
123 timing_gen_ctrl gen_ctrl;
124
125 reg_addr = (hi_u32 *)&(g_video_path_regs->tim_gen_ctrl.u32);
126 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
127 return gen_ctrl.bits.reg_timing_gen_en;
128 }
129
hdmi_reg_video_blank_en_set(unsigned int reg_video_blank_en)130 int hdmi_reg_video_blank_en_set(unsigned int reg_video_blank_en)
131 {
132 hi_u32 *reg_addr = NULL;
133 video_path_ctrl ctrl;
134
135 reg_addr = (hi_u32 *)&(g_video_path_regs->vid_path_ctrl.u32);
136 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
137 ctrl.bits.reg_video_blank_en = reg_video_blank_en;
138 hdmi_tx_reg_write(reg_addr, ctrl.u32);
139
140 return HI_SUCCESS;
141 }
142
hdmi_reg_video_blank_en_get(hi_void)143 hi_u32 hdmi_reg_video_blank_en_get(hi_void)
144 {
145 hi_u32 *reg_addr = NULL;
146 video_path_ctrl ctrl;
147
148 reg_addr = (hi_u32 *)&(g_video_path_regs->vid_path_ctrl.u32);
149 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
150 return ctrl.bits.reg_video_blank_en;
151 }
152
hdmi_reg_video_lp_disable_set(unsigned int reg_video_lp_disable)153 int hdmi_reg_video_lp_disable_set(unsigned int reg_video_lp_disable)
154 {
155 hi_u32 *reg_addr = NULL;
156 video_path_ctrl ctrl;
157
158 reg_addr = (hi_u32 *)&(g_video_path_regs->vid_path_ctrl.u32);
159 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
160 ctrl.bits.reg_video_lp_disable = reg_video_lp_disable;
161 hdmi_tx_reg_write(reg_addr, ctrl.u32);
162
163 return HI_SUCCESS;
164 }
165
hdmi_reg_video_lp_disable_get(hi_void)166 hi_u32 hdmi_reg_video_lp_disable_get(hi_void)
167 {
168 hi_u32 *reg_addr = NULL;
169 video_path_ctrl ctrl;
170
171 reg_addr = (hi_u32 *)&(g_video_path_regs->vid_path_ctrl.u32);
172 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
173 return ctrl.bits.reg_video_lp_disable;
174 }
175
hdmi_reg_cbar_pattern_sel_set(unsigned int cbar_pattern_sel)176 int hdmi_reg_cbar_pattern_sel_set(unsigned int cbar_pattern_sel)
177 {
178 hi_u32 *reg_addr = NULL;
179 pattern_gen_ctrll pattern_gen_ctrl;
180
181 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
182 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
183 pattern_gen_ctrl.bits.cbar_pattern_sel = cbar_pattern_sel;
184 hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32);
185
186 return HI_SUCCESS;
187 }
188
hdmi_reg_mask_pattern_en_set(unsigned int mask_pattern_en)189 int hdmi_reg_mask_pattern_en_set(unsigned int mask_pattern_en)
190 {
191 hi_u32 *reg_addr = NULL;
192 pattern_gen_ctrll gen_ctrl;
193
194 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
195 gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
196 gen_ctrl.bits.mask_pattern_en = mask_pattern_en;
197 hdmi_tx_reg_write(reg_addr, gen_ctrl.u32);
198
199 return HI_SUCCESS;
200 }
201
hdmi_reg_mask_pattern_en_get(hi_void)202 hi_u32 hdmi_reg_mask_pattern_en_get(hi_void)
203 {
204 hi_u32 *reg_addr = NULL;
205 pattern_gen_ctrll pattern_gen_ctrl;
206
207 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
208 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
209 return pattern_gen_ctrl.bits.mask_pattern_en;
210 }
211
hdmi_reg_square_pattern_en_set(unsigned int square_pattern_en)212 int hdmi_reg_square_pattern_en_set(unsigned int square_pattern_en)
213 {
214 hi_u32 *reg_addr = NULL;
215 pattern_gen_ctrll pattern_gen_ctrl;
216
217 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
218 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
219 pattern_gen_ctrl.bits.square_pattern_en = square_pattern_en;
220 hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32);
221
222 return HI_SUCCESS;
223 }
224
hdmi_reg_square_pattern_en_get(hi_void)225 hi_u32 hdmi_reg_square_pattern_en_get(hi_void)
226 {
227 hi_u32 *reg_addr = NULL;
228 pattern_gen_ctrll pattern_gen_ctrl;
229
230 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
231 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
232 return pattern_gen_ctrl.bits.square_pattern_en;
233 }
234
hdmi_reg_colorbar_en_set(unsigned int colorbar_en)235 int hdmi_reg_colorbar_en_set(unsigned int colorbar_en)
236 {
237 hi_u32 *reg_addr = NULL;
238 pattern_gen_ctrll pattern_gen_ctrl;
239
240 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
241 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
242 pattern_gen_ctrl.bits.colorbar_en = colorbar_en;
243 hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32);
244
245 return HI_SUCCESS;
246 }
247
hdmi_reg_colorbar_en_get(hi_void)248 hi_u32 hdmi_reg_colorbar_en_get(hi_void)
249 {
250 hi_u32 *reg_addr = NULL;
251 pattern_gen_ctrll pattern_gen_ctrl;
252
253 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
254 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
255
256 return pattern_gen_ctrl.bits.colorbar_en;
257 }
258
hdmi_reg_solid_pattern_en_set(unsigned int solid_pattern_en)259 int hdmi_reg_solid_pattern_en_set(unsigned int solid_pattern_en)
260 {
261 hi_u32 *reg_addr = NULL;
262 pattern_gen_ctrll pattern_gen_ctrl;
263
264 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
265 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
266 pattern_gen_ctrl.bits.solid_pattern_en = solid_pattern_en;
267 hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32);
268
269 return HI_SUCCESS;
270 }
271
hdmi_reg_solid_pattern_en_get(hi_void)272 hi_u32 hdmi_reg_solid_pattern_en_get(hi_void)
273 {
274 hi_u32 *reg_addr = NULL;
275 pattern_gen_ctrll pattern_gen_ctrl;
276
277 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
278 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
279 return pattern_gen_ctrl.bits.solid_pattern_en;
280 }
281
hdmi_reg_video_format_set(unsigned int video_format)282 int hdmi_reg_video_format_set(unsigned int video_format)
283 {
284 hi_u32 *reg_addr = NULL;
285 pattern_gen_ctrll pattern_gen_ctrl;
286
287 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
288 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
289 pattern_gen_ctrl.bits.video_format = video_format;
290 hdmi_tx_reg_write(reg_addr, pattern_gen_ctrl.u32);
291
292 return HI_SUCCESS;
293 }
294
hdmi_reg_video_format_get(hi_void)295 hi_u32 hdmi_reg_video_format_get(hi_void)
296 {
297 hi_u32 *reg_addr = NULL;
298 pattern_gen_ctrll pattern_gen_ctrl;
299
300 reg_addr = (hi_u32 *)&(g_video_path_regs->ptn_gen_ctrl.u32);
301 pattern_gen_ctrl.u32 = hdmi_tx_reg_read(reg_addr);
302
303 return pattern_gen_ctrl.bits.video_format;
304 }
305
hdmi_reg_solid_pattern_cr_set(unsigned int solid_pattern_cr)306 int hdmi_reg_solid_pattern_cr_set(unsigned int solid_pattern_cr)
307 {
308 hi_u32 *reg_addr = NULL;
309 solid_pattern_config config;
310
311 reg_addr = (hi_u32 *)&(g_video_path_regs->solid_ptn_ctrl.u32);
312 config.u32 = hdmi_tx_reg_read(reg_addr);
313 config.bits.solid_pattern_cr = solid_pattern_cr;
314 hdmi_tx_reg_write(reg_addr, config.u32);
315
316 return HI_SUCCESS;
317 }
318
hdmi_reg_solid_pattern_y_set(unsigned int solid_pattern_y)319 int hdmi_reg_solid_pattern_y_set(unsigned int solid_pattern_y)
320 {
321 hi_u32 *reg_addr = NULL;
322 solid_pattern_config config;
323
324 reg_addr = (hi_u32 *)&(g_video_path_regs->solid_ptn_ctrl.u32);
325 config.u32 = hdmi_tx_reg_read(reg_addr);
326 config.bits.solid_pattern_y = solid_pattern_y;
327 hdmi_tx_reg_write(reg_addr, config.u32);
328
329 return HI_SUCCESS;
330 }
331
hdmi_reg_solid_pattern_cb_set(unsigned int solid_pattern_cb)332 int hdmi_reg_solid_pattern_cb_set(unsigned int solid_pattern_cb)
333 {
334 hi_u32 *reg_addr = NULL;
335 solid_pattern_config config;
336
337 reg_addr = (hi_u32 *)&(g_video_path_regs->solid_ptn_ctrl.u32);
338 config.u32 = hdmi_tx_reg_read(reg_addr);
339 config.bits.solid_pattern_cb = solid_pattern_cb;
340 hdmi_tx_reg_write(reg_addr, config.u32);
341
342 return HI_SUCCESS;
343 }
344
hdmi_reg_fdt_status_clear_set(unsigned int fdt_status_clear)345 int hdmi_reg_fdt_status_clear_set(unsigned int fdt_status_clear)
346 {
347 hi_u32 *reg_addr = NULL;
348 format_det_config config;
349
350 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_det_cfg.u32);
351 config.u32 = hdmi_tx_reg_read(reg_addr);
352 config.bits.fdt_status_clear = fdt_status_clear;
353 hdmi_tx_reg_write(reg_addr, config.u32);
354
355 return HI_SUCCESS;
356 }
357
hdmi_reg_sync_polarity_force_set(unsigned int sync_polarity_force)358 int hdmi_reg_sync_polarity_force_set(unsigned int sync_polarity_force)
359 {
360 hi_u32 *reg_addr = NULL;
361 format_det_config config;
362
363 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_det_cfg.u32);
364 config.u32 = hdmi_tx_reg_read(reg_addr);
365 config.bits.sync_polarity_force = sync_polarity_force;
366 hdmi_tx_reg_write(reg_addr, config.u32);
367
368 return HI_SUCCESS;
369 }
370
hdmi_reg_vsync_polarity_get(hi_void)371 hi_u32 hdmi_reg_vsync_polarity_get(hi_void)
372 {
373 hi_u32 *reg_addr = NULL;
374 fdet_status status;
375
376 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_status.u32);
377 status.u32 = hdmi_tx_reg_read(reg_addr);
378
379 return status.bits.vsync_polarity;
380 }
381
hdmi_reg_hsync_polarity_get(hi_void)382 hi_u32 hdmi_reg_hsync_polarity_get(hi_void)
383 {
384 hi_u32 *reg_addr = NULL;
385 fdet_status status;
386
387 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_status.u32);
388 status.u32 = hdmi_tx_reg_read(reg_addr);
389
390 return status.bits.hsync_polarity;
391 }
392
hdmi_reg_interlaced_get(hi_void)393 hi_u32 hdmi_reg_interlaced_get(hi_void)
394 {
395 hi_u32 *reg_addr = NULL;
396 fdet_status status;
397
398 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_status.u32);
399 status.u32 = hdmi_tx_reg_read(reg_addr);
400
401 return status.bits.interlaced;
402 }
403
hdmi_reg_hsync_total_cnt_get(hi_void)404 hi_u32 hdmi_reg_hsync_total_cnt_get(hi_void)
405 {
406 hi_u32 *reg_addr = NULL;
407 fdet_hori_res tmp;
408
409 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_hori_res.u32);
410 tmp.u32 = hdmi_tx_reg_read(reg_addr);
411
412 return tmp.bits.hsync_total_cnt;
413 }
414
hdmi_reg_hsync_active_cnt_get(hi_void)415 hi_u32 hdmi_reg_hsync_active_cnt_get(hi_void)
416 {
417 hi_u32 *reg_addr = NULL;
418 fdet_hori_res tmp;
419
420 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_hori_res.u32);
421 tmp.u32 = hdmi_tx_reg_read(reg_addr);
422 return tmp.bits.hsync_active_cnt;
423 }
424
hdmi_reg_vsync_total_cnt_get(hi_void)425 hi_u32 hdmi_reg_vsync_total_cnt_get(hi_void)
426 {
427 hi_u32 *reg_addr = NULL;
428 fdet_hori_vert_res fdet_vert_res;
429
430 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_hori_vert_res.u32);
431 fdet_vert_res.u32 = hdmi_tx_reg_read(reg_addr);
432 return fdet_vert_res.bits.vsync_total_cnt;
433 }
434
hdmi_reg_vsync_active_cnt_get(hi_void)435 hi_u32 hdmi_reg_vsync_active_cnt_get(hi_void)
436 {
437 hi_u32 *reg_addr = NULL;
438 fdet_hori_vert_res fdet_vert_res;
439
440 reg_addr = (hi_u32 *)&(g_video_path_regs->fmt_dect_hori_vert_res.u32);
441 fdet_vert_res.u32 = hdmi_tx_reg_read(reg_addr);
442
443 return fdet_vert_res.bits.vsync_active_cnt;
444 }
445
hdmi_reg_dwsm_vert_bypass_get(hi_void)446 hi_u32 hdmi_reg_dwsm_vert_bypass_get(hi_void)
447 {
448 hi_u32 *reg_addr = NULL;
449 video_dwsm_ctrl ctrl;
450
451 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
452 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
453
454 return ctrl.bits.reg_dwsm_vert_byp;
455 }
456
hdmi_reg_dwsm_vert_en_get(hi_void)457 hi_u32 hdmi_reg_dwsm_vert_en_get(hi_void)
458 {
459 hi_u32 *reg_addr = NULL;
460 video_dwsm_ctrl ctrl;
461
462 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
463 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
464
465 return ctrl.bits.reg_dwsm_vert_en;
466 }
467
hdmi_reg_hori_filter_en_get(hi_void)468 hi_u32 hdmi_reg_hori_filter_en_get(hi_void)
469 {
470 hi_u32 *reg_addr = NULL;
471
472 video_dwsm_ctrl ctrl;
473 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
474 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
475 return ctrl.bits.reg_hori_filter_en;
476 }
477
hdmi_reg_dwsm_hori_en_get(hi_void)478 hi_u32 hdmi_reg_dwsm_hori_en_get(hi_void)
479 {
480 hi_u32 *reg_addr = NULL;
481 video_dwsm_ctrl ctrl;
482
483 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
484 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
485
486 return ctrl.bits.reg_dwsm_hori_en;
487 }
488
hdmi_reg_pxl_div_en_get(hi_void)489 hi_u32 hdmi_reg_pxl_div_en_get(hi_void)
490 {
491 hi_u32 *reg_addr = NULL;
492 data_align_ctrl ctrl;
493
494 reg_addr = (hi_u32 *)&(g_video_path_regs->align_ctrl.u32);
495 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
496
497 return ctrl.bits.reg_pxl_div_en;
498 }
499
hdmi_reg_demux_420_en_get(hi_void)500 hi_u32 hdmi_reg_demux_420_en_get(hi_void)
501 {
502 hi_u32 *reg_addr = NULL;
503 data_align_ctrl ctrl;
504
505 reg_addr = (hi_u32 *)&(g_video_path_regs->align_ctrl.u32);
506 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
507
508 return ctrl.bits.reg_demux_420_en;
509 }
510
hdmi_reg_inver_sync_get(hi_void)511 hi_u32 hdmi_reg_inver_sync_get(hi_void)
512 {
513 hi_u32 *reg_addr = NULL;
514 video_dmux_ctrl ctrl;
515
516 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
517 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
518
519 return ctrl.bits.reg_inver_sync;
520 }
521
hdmi_reg_vmux_cr_sel_get(hi_void)522 hi_u32 hdmi_reg_vmux_cr_sel_get(hi_void)
523 {
524 hi_u32 *reg_addr = NULL;
525 video_dmux_ctrl ctrl;
526
527 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
528 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
529
530 return ctrl.bits.reg_vmux_cr_sel;
531 }
532
hdmi_reg_vmux_cb_sel_get(hi_void)533 hi_u32 hdmi_reg_vmux_cb_sel_get(hi_void)
534 {
535 hi_u32 *reg_addr = NULL;
536 video_dmux_ctrl ctrl;
537
538 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
539 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
540
541 return ctrl.bits.reg_vmux_cb_sel;
542 }
543
hdmi_reg_vmux_y_sel_get(hi_void)544 hi_u32 hdmi_reg_vmux_y_sel_get(hi_void)
545 {
546 hi_u32 *reg_addr = NULL;
547 video_dmux_ctrl ctrl;
548
549 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
550 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
551
552 return ctrl.bits.reg_vmux_y_sel;
553 }
554
hdmi_reg_dither_mode_get(hi_void)555 hi_u32 hdmi_reg_dither_mode_get(hi_void)
556 {
557 hi_u32 *reg_addr = NULL;
558 dither_config config;
559
560 reg_addr = (hi_u32 *)&(g_video_path_regs->dither_cfg.u32);
561 config.u32 = hdmi_tx_reg_read(reg_addr);
562
563 return config.bits.dither_mode;
564 }
565
hdmi_reg_dither_rnd_bypass_get(hi_void)566 hi_u32 hdmi_reg_dither_rnd_bypass_get(hi_void)
567 {
568 hi_u32 *reg_addr = NULL;
569 dither_config config;
570
571 reg_addr = (hi_u32 *)&(g_video_path_regs->dither_cfg.u32);
572 config.u32 = hdmi_tx_reg_read(reg_addr);
573
574 return config.bits.dither_rnd_byp;
575 }
576
hdmi_reg_csc_en_get(hi_void)577 hi_u32 hdmi_reg_csc_en_get(hi_void)
578 {
579 hi_u32 *reg_addr = NULL;
580 multi_csc_ctrl ctrl;
581
582 reg_addr = (hi_u32 *)&(g_video_path_regs->csc_ctrl.u32);
583 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
584
585 return ctrl.bits.reg_csc_en;
586 }
587
hdmi_reg_csc_mode_get(hi_void)588 hi_u32 hdmi_reg_csc_mode_get(hi_void)
589 {
590 hi_u32 *reg_addr = NULL;
591 multi_csc_ctrl ctrl;
592
593 reg_addr = (hi_u32 *)&(g_video_path_regs->csc_ctrl.u32);
594 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
595 return ctrl.bits.reg_csc_mode;
596 }
597
hdmi_reg_dither_mode_set(unsigned int dither_mode)598 int hdmi_reg_dither_mode_set(unsigned int dither_mode)
599 {
600 hi_u32 *reg_addr = NULL;
601 dither_config config;
602
603 reg_addr = (hi_u32 *)&(g_video_path_regs->dither_cfg.u32);
604 config.u32 = hdmi_tx_reg_read(reg_addr);
605 config.bits.dither_mode = dither_mode;
606 hdmi_tx_reg_write(reg_addr, config.u32);
607
608 return HI_SUCCESS;
609 }
610
hdmi_reg_dither_rnd_bypass_set(unsigned int dither_rnd_byp)611 int hdmi_reg_dither_rnd_bypass_set(unsigned int dither_rnd_byp)
612 {
613 hi_u32 *reg_addr = NULL;
614 dither_config config;
615
616 reg_addr = (hi_u32 *)&(g_video_path_regs->dither_cfg.u32);
617 config.u32 = hdmi_tx_reg_read(reg_addr);
618 config.bits.dither_rnd_byp = dither_rnd_byp;
619 hdmi_tx_reg_write(reg_addr, config.u32);
620
621 return HI_SUCCESS;
622 }
623
hdmi_reg_csc_mode_set(unsigned int reg_csc_mode)624 int hdmi_reg_csc_mode_set(unsigned int reg_csc_mode)
625 {
626 hi_u32 *reg_addr = NULL;
627 multi_csc_ctrl ctrl;
628
629 reg_addr = (hi_u32 *)&(g_video_path_regs->csc_ctrl.u32);
630 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
631 ctrl.bits.reg_csc_mode = reg_csc_mode;
632 hdmi_tx_reg_write(reg_addr, ctrl.u32);
633
634 return HI_SUCCESS;
635 }
636
hdmi_reg_csc_saturate_en_set(unsigned int reg_csc_saturate_en)637 int hdmi_reg_csc_saturate_en_set(unsigned int reg_csc_saturate_en)
638 {
639 hi_u32 *reg_addr = NULL;
640 multi_csc_ctrl ctrl;
641
642 reg_addr = (hi_u32 *)&(g_video_path_regs->csc_ctrl.u32);
643 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
644 ctrl.bits.reg_csc_saturate_en = reg_csc_saturate_en;
645 hdmi_tx_reg_write(reg_addr, ctrl.u32);
646
647 return HI_SUCCESS;
648 }
649
hdmi_reg_csc_en_set(unsigned int reg_csc_en)650 int hdmi_reg_csc_en_set(unsigned int reg_csc_en)
651 {
652 hi_u32 *reg_addr = NULL;
653 multi_csc_ctrl ctrl;
654
655 reg_addr = (hi_u32 *)&(g_video_path_regs->csc_ctrl.u32);
656 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
657 ctrl.bits.reg_csc_en = reg_csc_en;
658 hdmi_tx_reg_write(reg_addr, ctrl.u32);
659
660 return HI_SUCCESS;
661 }
662
hdmi_reg_dwsm_vert_bypass_set(unsigned int reg_dwsm_vert_byp)663 int hdmi_reg_dwsm_vert_bypass_set(unsigned int reg_dwsm_vert_byp)
664 {
665 hi_u32 *reg_addr = NULL;
666 video_dwsm_ctrl ctrl;
667
668 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
669 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
670 ctrl.bits.reg_dwsm_vert_byp = reg_dwsm_vert_byp;
671 hdmi_tx_reg_write(reg_addr, ctrl.u32);
672
673 return HI_SUCCESS;
674 }
675
hdmi_reg_dwsm_vert_en_set(unsigned int reg_dwsm_vert_en)676 int hdmi_reg_dwsm_vert_en_set(unsigned int reg_dwsm_vert_en)
677 {
678 hi_u32 *reg_addr = NULL;
679 video_dwsm_ctrl ctrl;
680
681 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
682 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
683 ctrl.bits.reg_dwsm_vert_en = reg_dwsm_vert_en;
684 hdmi_tx_reg_write(reg_addr, ctrl.u32);
685
686 return HI_SUCCESS;
687 }
688
hdmi_reg_hori_filter_en_set(unsigned int reg_hori_filter_en)689 int hdmi_reg_hori_filter_en_set(unsigned int reg_hori_filter_en)
690 {
691 hi_u32 *reg_addr = NULL;
692 video_dwsm_ctrl ctrl;
693
694 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
695 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
696 ctrl.bits.reg_hori_filter_en = reg_hori_filter_en;
697 hdmi_tx_reg_write(reg_addr, ctrl.u32);
698
699 return HI_SUCCESS;
700 }
701
hdmi_reg_dwsm_hori_en_set(unsigned int reg_dwsm_hori_en)702 int hdmi_reg_dwsm_hori_en_set(unsigned int reg_dwsm_hori_en)
703 {
704 hi_u32 *reg_addr = NULL;
705 video_dwsm_ctrl ctrl;
706
707 reg_addr = (hi_u32 *)&(g_video_path_regs->dwsm_ctrl.u32);
708 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
709 ctrl.bits.reg_dwsm_hori_en = reg_dwsm_hori_en;
710 hdmi_tx_reg_write(reg_addr, ctrl.u32);
711
712 return HI_SUCCESS;
713 }
714
hdmi_reg_pxl_div_en_set(unsigned int reg_pxl_div_en)715 int hdmi_reg_pxl_div_en_set(unsigned int reg_pxl_div_en)
716 {
717 hi_u32 *reg_addr = NULL;
718 data_align_ctrl ctrl;
719
720 reg_addr = (hi_u32 *)&(g_video_path_regs->align_ctrl.u32);
721 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
722 ctrl.bits.reg_pxl_div_en = reg_pxl_div_en;
723 hdmi_tx_reg_write(reg_addr, ctrl.u32);
724
725 return HI_SUCCESS;
726 }
727
hdmi_reg_demux_420_en_set(unsigned int reg_demux_420_en)728 int hdmi_reg_demux_420_en_set(unsigned int reg_demux_420_en)
729 {
730 hi_u32 *reg_addr = NULL;
731 data_align_ctrl ctrl;
732
733 reg_addr = (hi_u32 *)&(g_video_path_regs->align_ctrl.u32);
734 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
735 ctrl.bits.reg_demux_420_en = reg_demux_420_en;
736 hdmi_tx_reg_write(reg_addr, ctrl.u32);
737
738 return HI_SUCCESS;
739 }
740
hdmi_reg_inver_sync_set(unsigned int reg_inver_sync)741 int hdmi_reg_inver_sync_set(unsigned int reg_inver_sync)
742 {
743 hi_u32 *reg_addr = NULL;
744 video_dmux_ctrl ctrl;
745
746 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
747 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
748 ctrl.bits.reg_inver_sync = reg_inver_sync;
749 hdmi_tx_reg_write(reg_addr, ctrl.u32);
750
751 return HI_SUCCESS;
752 }
753
hdmi_reg_syncmask_en_set(unsigned int reg_syncmask_en)754 int hdmi_reg_syncmask_en_set(unsigned int reg_syncmask_en)
755 {
756 hi_u32 *reg_addr = NULL;
757 video_dmux_ctrl ctrl;
758
759 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
760 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
761 ctrl.bits.reg_syncmask_en = reg_syncmask_en;
762 hdmi_tx_reg_write(reg_addr, ctrl.u32);
763
764 return HI_SUCCESS;
765 }
766
hdmi_reg_vmux_cr_sel_set(unsigned int reg_vmux_cr_sel)767 int hdmi_reg_vmux_cr_sel_set(unsigned int reg_vmux_cr_sel)
768 {
769 hi_u32 *reg_addr = NULL;
770 video_dmux_ctrl ctrl;
771
772 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
773 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
774 ctrl.bits.reg_vmux_cr_sel = reg_vmux_cr_sel;
775 hdmi_tx_reg_write(reg_addr, ctrl.u32);
776
777 return HI_SUCCESS;
778 }
779
hdmi_reg_vmux_cb_sel_set(unsigned int reg_vmux_cb_sel)780 int hdmi_reg_vmux_cb_sel_set(unsigned int reg_vmux_cb_sel)
781 {
782 hi_u32 *reg_addr = NULL;
783 video_dmux_ctrl ctrl;
784
785 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
786 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
787 ctrl.bits.reg_vmux_cb_sel = reg_vmux_cb_sel;
788 hdmi_tx_reg_write(reg_addr, ctrl.u32);
789
790 return HI_SUCCESS;
791 }
792
hdmi_reg_vmux_y_sel_set(unsigned int reg_vmux_y_sel)793 int hdmi_reg_vmux_y_sel_set(unsigned int reg_vmux_y_sel)
794 {
795 hi_u32 *reg_addr = NULL;
796 video_dmux_ctrl ctrl;
797
798 reg_addr = (hi_u32 *)&(g_video_path_regs->dmux_ctrl.u32);
799 ctrl.u32 = hdmi_tx_reg_read(reg_addr);
800 ctrl.bits.reg_vmux_y_sel = reg_vmux_y_sel;
801 hdmi_tx_reg_write(reg_addr, ctrl.u32);
802
803 return HI_SUCCESS;
804 }
805
806