1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Extended Trap data component interface file. 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: etd.h 813064 2019-04-03 11:29:38Z $ 29 */ 30 31 #ifndef _ETD_H_ 32 #define _ETD_H_ 33 34 #if defined(ETD) && !defined(WLETD) 35 #include <hnd_trap.h> 36 #endif // endif 37 #include <bcmutils.h> 38 /* Tags for structures being used by etd info iovar. 39 * Related structures are defined in wlioctl.h. 40 */ 41 #define ETD_TAG_JOIN_CLASSIFICATION_INFO 10 /* general information about join request */ 42 #define ETD_TAG_JOIN_TARGET_CLASSIFICATION_INFO 11 /* per target (AP) join information */ 43 #define ETD_TAG_ASSOC_STATE 12 /* current state of the Device association state machine */ 44 #define ETD_TAG_CHANNEL 13 /* current channel on which the association was performed */ 45 #define ETD_TAG_TOTAL_NUM_OF_JOIN_ATTEMPTS 14 /* number of join attempts (bss_retries) */ 46 47 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1 3 48 #define PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2 6 49 50 #ifndef _LANGUAGE_ASSEMBLY 51 52 #define HND_EXTENDED_TRAP_VERSION 1 53 #define HND_EXTENDED_TRAP_BUFLEN 512 54 55 typedef struct hnd_ext_trap_hdr { 56 uint8 version; /* Extended trap version info */ 57 uint8 reserved; /* currently unused */ 58 uint16 len; /* Length of data excluding this header */ 59 uint8 data[]; /* TLV data */ 60 } hnd_ext_trap_hdr_t; 61 62 typedef enum { 63 TAG_TRAP_NONE = 0, /* None trap type */ 64 TAG_TRAP_SIGNATURE = 1, /* Processor register dumps */ 65 TAG_TRAP_STACK = 2, /* Processor stack dump (possible code locations) */ 66 TAG_TRAP_MEMORY = 3, /* Memory subsystem dump */ 67 TAG_TRAP_DEEPSLEEP = 4, /* Deep sleep health check failures */ 68 TAG_TRAP_PSM_WD = 5, /* PSM watchdog information */ 69 TAG_TRAP_PHY = 6, /* Phy related issues */ 70 TAG_TRAP_BUS = 7, /* Bus level issues */ 71 TAG_TRAP_MAC_SUSP = 8, /* Mac level suspend issues */ 72 TAG_TRAP_BACKPLANE = 9, /* Backplane related errors */ 73 /* Values 10 through 14 are in use by etd_data info iovar */ 74 TAG_TRAP_PCIE_Q = 15, /* PCIE Queue state during memory trap */ 75 TAG_TRAP_WLC_STATE = 16, /* WLAN state during memory trap */ 76 TAG_TRAP_MAC_WAKE = 17, /* Mac level wake issues */ 77 TAG_TRAP_PHYTXERR_THRESH = 18, /* Phy Tx Err */ 78 TAG_TRAP_HC_DATA = 19, /* Data collected by HC module */ 79 TAG_TRAP_LOG_DATA = 20, 80 TAG_TRAP_CODE = 21, /* The trap type */ 81 TAG_TRAP_HMAP = 22, /* HMAP violation Address and Info */ 82 TAG_TRAP_PCIE_ERR_ATTN = 23, /* PCIE error attn log */ 83 TAG_TRAP_AXI_ERROR = 24, /* AXI Error */ 84 TAG_TRAP_AXI_HOST_INFO = 25, /* AXI Host log */ 85 TAG_TRAP_AXI_SR_ERROR = 26, /* AXI SR error log */ 86 TAG_TRAP_LAST /* This must be the last entry */ 87 } hnd_ext_tag_trap_t; 88 89 typedef struct hnd_ext_trap_bp_err 90 { 91 uint32 error; 92 uint32 coreid; 93 uint32 baseaddr; 94 uint32 ioctrl; 95 uint32 iostatus; 96 uint32 resetctrl; 97 uint32 resetstatus; 98 uint32 resetreadid; 99 uint32 resetwriteid; 100 uint32 errlogctrl; 101 uint32 errlogdone; 102 uint32 errlogstatus; 103 uint32 errlogaddrlo; 104 uint32 errlogaddrhi; 105 uint32 errlogid; 106 uint32 errloguser; 107 uint32 errlogflags; 108 uint32 itipoobaout; 109 uint32 itipoobbout; 110 uint32 itipoobcout; 111 uint32 itipoobdout; 112 } hnd_ext_trap_bp_err_t; 113 114 #define HND_EXT_TRAP_AXISR_INFO_VER_1 1 115 typedef struct hnd_ext_trap_axi_sr_err_v1 116 { 117 uint8 version; 118 uint8 pad[3]; 119 uint32 error; 120 uint32 coreid; 121 uint32 baseaddr; 122 uint32 ioctrl; 123 uint32 iostatus; 124 uint32 resetctrl; 125 uint32 resetstatus; 126 uint32 resetreadid; 127 uint32 resetwriteid; 128 uint32 errlogctrl; 129 uint32 errlogdone; 130 uint32 errlogstatus; 131 uint32 errlogaddrlo; 132 uint32 errlogaddrhi; 133 uint32 errlogid; 134 uint32 errloguser; 135 uint32 errlogflags; 136 uint32 itipoobaout; 137 uint32 itipoobbout; 138 uint32 itipoobcout; 139 uint32 itipoobdout; 140 141 /* axi_sr_issue_debug */ 142 uint32 sr_pwr_control; 143 uint32 sr_corereset_wrapper_main; 144 uint32 sr_corereset_wrapper_aux; 145 uint32 sr_main_gci_status_0; 146 uint32 sr_aux_gci_status_0; 147 uint32 sr_dig_gci_status_0; 148 } hnd_ext_trap_axi_sr_err_v1_t; 149 150 #define HND_EXT_TRAP_PSMWD_INFO_VER 1 151 typedef struct hnd_ext_trap_psmwd_v1 { 152 uint16 xtag; 153 uint16 version; /* version of the information following this */ 154 uint32 i32_maccontrol; 155 uint32 i32_maccommand; 156 uint32 i32_macintstatus; 157 uint32 i32_phydebug; 158 uint32 i32_clk_ctl_st; 159 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V1]; 160 uint16 i16_0x1a8; /* gated clock en */ 161 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 162 uint16 i16_0x408; /* Rx ctrl 1 */ 163 uint16 i16_0x41a; /* Rxe Status 1 */ 164 uint16 i16_0x41c; /* Rxe Status 2 */ 165 uint16 i16_0x424; /* rcv wrd count 0 */ 166 uint16 i16_0x426; /* rcv wrd count 1 */ 167 uint16 i16_0x456; /* RCV_LFIFO_STS */ 168 uint16 i16_0x480; /* PSM_SLP_TMR */ 169 uint16 i16_0x490; /* PSM BRC */ 170 uint16 i16_0x500; /* TXE CTRL */ 171 uint16 i16_0x50e; /* TXE Status */ 172 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 173 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 174 uint16 i16_0x690; /* IFS Stat */ 175 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 176 uint16 i16_0x694; /* IFS_TX_DUR */ 177 uint16 i16_0x6a0; /* SLow_CTL */ 178 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 179 uint16 i16_0x8c0; /* Dagg ctrl */ 180 uint16 shm_prewds_cnt; 181 uint16 shm_txtplufl_cnt; 182 uint16 shm_txphyerr_cnt; 183 uint16 pad; 184 } hnd_ext_trap_psmwd_v1_t; 185 186 typedef struct hnd_ext_trap_psmwd { 187 uint16 xtag; 188 uint16 version; /* version of the information following this */ 189 uint32 i32_maccontrol; 190 uint32 i32_maccommand; 191 uint32 i32_macintstatus; 192 uint32 i32_phydebug; 193 uint32 i32_clk_ctl_st; 194 uint32 i32_psmdebug[PSMDBG_REG_READ_CNT_FOR_PSMWDTRAP_V2]; 195 uint16 i16_0x4b8; /* psm_brwk_0 */ 196 uint16 i16_0x4ba; /* psm_brwk_1 */ 197 uint16 i16_0x4bc; /* psm_brwk_2 */ 198 uint16 i16_0x4be; /* psm_brwk_2 */ 199 uint16 i16_0x1a8; /* gated clock en */ 200 uint16 i16_0x406; /* Rcv Fifo Ctrl */ 201 uint16 i16_0x408; /* Rx ctrl 1 */ 202 uint16 i16_0x41a; /* Rxe Status 1 */ 203 uint16 i16_0x41c; /* Rxe Status 2 */ 204 uint16 i16_0x424; /* rcv wrd count 0 */ 205 uint16 i16_0x426; /* rcv wrd count 1 */ 206 uint16 i16_0x456; /* RCV_LFIFO_STS */ 207 uint16 i16_0x480; /* PSM_SLP_TMR */ 208 uint16 i16_0x500; /* TXE CTRL */ 209 uint16 i16_0x50e; /* TXE Status */ 210 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 211 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 212 uint16 i16_0x690; /* IFS Stat */ 213 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 214 uint16 i16_0x694; /* IFS_TX_DUR */ 215 uint16 i16_0x6a0; /* SLow_CTL */ 216 uint16 i16_0x490; /* psm_brc */ 217 uint16 i16_0x4da; /* psm_brc_1 */ 218 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 219 uint16 i16_0x8c0; /* Dagg ctrl */ 220 uint16 shm_prewds_cnt; 221 uint16 shm_txtplufl_cnt; 222 uint16 shm_txphyerr_cnt; 223 } hnd_ext_trap_psmwd_t; 224 225 #define HEAP_HISTOGRAM_DUMP_LEN 6 226 #define HEAP_MAX_SZ_BLKS_LEN 2 227 228 /* Ignore chunks for which there are fewer than this many instances, irrespective of size */ 229 #define HEAP_HISTOGRAM_INSTANCE_MIN 4 230 231 /* 232 * Use the last two length values for chunks larger than this, or when we run out of 233 * histogram entries (because we have too many different sized chunks) to store "other" 234 */ 235 #define HEAP_HISTOGRAM_SPECIAL 0xfffeu 236 237 #define HEAP_HISTOGRAM_GRTR256K 0xffffu 238 239 typedef struct hnd_ext_trap_heap_err { 240 uint32 arena_total; 241 uint32 heap_free; 242 uint32 heap_inuse; 243 uint32 mf_count; 244 uint32 stack_lwm; 245 uint16 heap_histogm[HEAP_HISTOGRAM_DUMP_LEN * 2]; /* size/number */ 246 uint16 max_sz_free_blk[HEAP_MAX_SZ_BLKS_LEN]; 247 } hnd_ext_trap_heap_err_t; 248 249 #define MEM_TRAP_NUM_WLC_TX_QUEUES 6 250 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V2 2 251 252 typedef struct hnd_ext_trap_wlc_mem_err { 253 uint8 instance; 254 uint8 associated; 255 uint8 soft_ap_client_cnt; 256 uint8 peer_cnt; 257 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 258 } hnd_ext_trap_wlc_mem_err_t; 259 260 typedef struct hnd_ext_trap_wlc_mem_err_v2 { 261 uint16 version; 262 uint16 pad; 263 uint8 instance; 264 uint8 stas_associated; 265 uint8 aps_associated; 266 uint8 soft_ap_client_cnt; 267 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 268 } hnd_ext_trap_wlc_mem_err_v2_t; 269 270 #define HND_EXT_TRAP_WLC_MEM_ERR_VER_V3 3 271 272 typedef struct hnd_ext_trap_wlc_mem_err_v3 { 273 uint8 version; 274 uint8 instance; 275 uint8 stas_associated; 276 uint8 aps_associated; 277 uint8 soft_ap_client_cnt; 278 uint8 peer_cnt; 279 uint16 txqueue_len[MEM_TRAP_NUM_WLC_TX_QUEUES]; 280 } hnd_ext_trap_wlc_mem_err_v3_t; 281 282 typedef struct hnd_ext_trap_pcie_mem_err { 283 uint16 d2h_queue_len; 284 uint16 d2h_req_queue_len; 285 } hnd_ext_trap_pcie_mem_err_t; 286 287 #define MAX_DMAFIFO_ENTRIES_V1 1 288 #define MAX_DMAFIFO_DESC_ENTRIES_V1 2 289 #define HND_EXT_TRAP_AXIERROR_SIGNATURE 0xbabebabe 290 #define HND_EXT_TRAP_AXIERROR_VERSION_1 1 291 292 /* Structure to collect debug info of descriptor entry for dma channel on encountering AXI Error */ 293 /* Below three structures are dependant, any change will bump version of all the three */ 294 295 typedef struct hnd_ext_trap_desc_entry_v1 { 296 uint32 ctrl1; /* descriptor entry at din < misc control bits > */ 297 uint32 ctrl2; /* descriptor entry at din <buffer count and address extension> */ 298 uint32 addrlo; /* descriptor entry at din <address of data buffer, bits 31:0> */ 299 uint32 addrhi; /* descriptor entry at din <address of data buffer, bits 63:32> */ 300 } dma_dentry_v1_t; 301 302 /* Structure to collect debug info about a dma channel on encountering AXI Error */ 303 typedef struct hnd_ext_trap_dma_fifo_v1 { 304 uint8 valid; /* no of valid desc entries filled, non zero = fifo entry valid */ 305 uint8 direction; /* TX=1, RX=2, currently only using TX */ 306 uint16 index; /* Index of the DMA channel in system */ 307 uint32 dpa; /* Expected Address of Descriptor table from software state */ 308 uint32 desc_lo; /* Low Address of Descriptor table programmed in DMA register */ 309 uint32 desc_hi; /* High Address of Descriptor table programmed in DMA register */ 310 uint16 din; /* rxin / txin */ 311 uint16 dout; /* rxout / txout */ 312 dma_dentry_v1_t dentry[MAX_DMAFIFO_DESC_ENTRIES_V1]; /* Descriptor Entires */ 313 } dma_fifo_v1_t; 314 315 typedef struct hnd_ext_trap_axi_error_v1 { 316 uint8 version; /* version = 1 */ 317 uint8 dma_fifo_valid_count; /* Number of valid dma_fifo entries */ 318 uint16 length; /* length of whole structure */ 319 uint32 signature; /* indicate that its filled with AXI Error data */ 320 uint32 axi_errorlog_status; /* errlog_status from slave wrapper */ 321 uint32 axi_errorlog_core; /* errlog_core from slave wrapper */ 322 uint32 axi_errorlog_lo; /* errlog_lo from slave wrapper */ 323 uint32 axi_errorlog_hi; /* errlog_hi from slave wrapper */ 324 uint32 axi_errorlog_id; /* errlog_id from slave wrapper */ 325 dma_fifo_v1_t dma_fifo[MAX_DMAFIFO_ENTRIES_V1]; 326 } hnd_ext_trap_axi_error_v1_t; 327 328 #define HND_EXT_TRAP_MACSUSP_INFO_VER 1 329 typedef struct hnd_ext_trap_macsusp { 330 uint16 xtag; 331 uint8 version; /* version of the information following this */ 332 uint8 trap_reason; 333 uint32 i32_maccontrol; 334 uint32 i32_maccommand; 335 uint32 i32_macintstatus; 336 uint32 i32_phydebug[4]; 337 uint32 i32_psmdebug[8]; 338 uint16 i16_0x41a; /* Rxe Status 1 */ 339 uint16 i16_0x41c; /* Rxe Status 2 */ 340 uint16 i16_0x490; /* PSM BRC */ 341 uint16 i16_0x50e; /* TXE Status */ 342 uint16 i16_0x55e; /* TXE_xmtdmabusy */ 343 uint16 i16_0x566; /* TXE_XMTfifosuspflush */ 344 uint16 i16_0x690; /* IFS Stat */ 345 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 346 uint16 i16_0x694; /* IFS_TX_DUR */ 347 uint16 i16_0x7c0; /* WEP CTL */ 348 uint16 i16_0x838; /* TXE_AQM fifo Ready */ 349 uint16 i16_0x880; /* MHP_status */ 350 uint16 shm_prewds_cnt; 351 uint16 shm_ucode_dbgst; 352 } hnd_ext_trap_macsusp_t; 353 354 #define HND_EXT_TRAP_MACENAB_INFO_VER 1 355 typedef struct hnd_ext_trap_macenab { 356 uint16 xtag; 357 uint8 version; /* version of the information following this */ 358 uint8 trap_reason; 359 uint32 i32_maccontrol; 360 uint32 i32_maccommand; 361 uint32 i32_macintstatus; 362 uint32 i32_psmdebug[8]; 363 uint32 i32_clk_ctl_st; 364 uint32 i32_powerctl; 365 uint16 i16_0x1a8; /* gated clock en */ 366 uint16 i16_0x480; /* PSM_SLP_TMR */ 367 uint16 i16_0x490; /* PSM BRC */ 368 uint16 i16_0x600; /* TSF CTL */ 369 uint16 i16_0x690; /* IFS Stat */ 370 uint16 i16_0x692; /* IFS_MEDBUSY_CTR */ 371 uint16 i16_0x6a0; /* SLow_CTL */ 372 uint16 i16_0x6a6; /* SLow_FRAC */ 373 uint16 i16_0x6a8; /* fast power up delay */ 374 uint16 i16_0x6aa; /* SLow_PER */ 375 uint16 shm_ucode_dbgst; 376 uint16 PAD; 377 } hnd_ext_trap_macenab_t; 378 379 #define HND_EXT_TRAP_PHY_INFO_VER_1 (1) 380 typedef struct hnd_ext_trap_phydbg { 381 uint16 err; 382 uint16 RxFeStatus; 383 uint16 TxFIFOStatus0; 384 uint16 TxFIFOStatus1; 385 uint16 RfseqMode; 386 uint16 RfseqStatus0; 387 uint16 RfseqStatus1; 388 uint16 RfseqStatus_Ocl; 389 uint16 RfseqStatus_Ocl1; 390 uint16 OCLControl1; 391 uint16 TxError; 392 uint16 bphyTxError; 393 uint16 TxCCKError; 394 uint16 TxCtrlWrd0; 395 uint16 TxCtrlWrd1; 396 uint16 TxCtrlWrd2; 397 uint16 TxLsig0; 398 uint16 TxLsig1; 399 uint16 TxVhtSigA10; 400 uint16 TxVhtSigA11; 401 uint16 TxVhtSigA20; 402 uint16 TxVhtSigA21; 403 uint16 txPktLength; 404 uint16 txPsdulengthCtr; 405 uint16 gpioClkControl; 406 uint16 gpioSel; 407 uint16 pktprocdebug; 408 uint16 PAD; 409 uint32 gpioOut[3]; 410 } hnd_ext_trap_phydbg_t; 411 412 /* unique IDs for separate cores in SI */ 413 #define REGDUMP_MASK_MAC0 BCM_BIT(1) 414 #define REGDUMP_MASK_ARM BCM_BIT(2) 415 #define REGDUMP_MASK_PCIE BCM_BIT(3) 416 #define REGDUMP_MASK_MAC1 BCM_BIT(4) 417 #define REGDUMP_MASK_PMU BCM_BIT(5) 418 419 typedef struct { 420 uint16 reg_offset; 421 uint16 core_mask; 422 } reg_dump_config_t; 423 424 #define HND_EXT_TRAP_PHY_INFO_VER 2 425 typedef struct hnd_ext_trap_phydbg_v2 { 426 uint8 version; 427 uint8 len; 428 uint16 err; 429 uint16 RxFeStatus; 430 uint16 TxFIFOStatus0; 431 uint16 TxFIFOStatus1; 432 uint16 RfseqMode; 433 uint16 RfseqStatus0; 434 uint16 RfseqStatus1; 435 uint16 RfseqStatus_Ocl; 436 uint16 RfseqStatus_Ocl1; 437 uint16 OCLControl1; 438 uint16 TxError; 439 uint16 bphyTxError; 440 uint16 TxCCKError; 441 uint16 TxCtrlWrd0; 442 uint16 TxCtrlWrd1; 443 uint16 TxCtrlWrd2; 444 uint16 TxLsig0; 445 uint16 TxLsig1; 446 uint16 TxVhtSigA10; 447 uint16 TxVhtSigA11; 448 uint16 TxVhtSigA20; 449 uint16 TxVhtSigA21; 450 uint16 txPktLength; 451 uint16 txPsdulengthCtr; 452 uint16 gpioClkControl; 453 uint16 gpioSel; 454 uint16 pktprocdebug; 455 uint32 gpioOut[3]; 456 uint32 additional_regs[1]; 457 } hnd_ext_trap_phydbg_v2_t; 458 459 #define HND_EXT_TRAP_PHY_INFO_VER_3 (3) 460 typedef struct hnd_ext_trap_phydbg_v3 { 461 uint8 version; 462 uint8 len; 463 uint16 err; 464 uint16 RxFeStatus; 465 uint16 TxFIFOStatus0; 466 uint16 TxFIFOStatus1; 467 uint16 RfseqMode; 468 uint16 RfseqStatus0; 469 uint16 RfseqStatus1; 470 uint16 RfseqStatus_Ocl; 471 uint16 RfseqStatus_Ocl1; 472 uint16 OCLControl1; 473 uint16 TxError; 474 uint16 bphyTxError; 475 uint16 TxCCKError; 476 uint16 TxCtrlWrd0; 477 uint16 TxCtrlWrd1; 478 uint16 TxCtrlWrd2; 479 uint16 TxLsig0; 480 uint16 TxLsig1; 481 uint16 TxVhtSigA10; 482 uint16 TxVhtSigA11; 483 uint16 TxVhtSigA20; 484 uint16 TxVhtSigA21; 485 uint16 txPktLength; 486 uint16 txPsdulengthCtr; 487 uint16 gpioClkControl; 488 uint16 gpioSel; 489 uint16 pktprocdebug; 490 uint32 gpioOut[3]; 491 uint16 HESigURateFlagStatus; 492 uint16 HESigUsRateFlagStatus; 493 uint32 additional_regs[1]; 494 } hnd_ext_trap_phydbg_v3_t; 495 496 /* Phy TxErr Dump Structure */ 497 #define HND_EXT_TRAP_PHYTXERR_INFO_VER 1 498 #define HND_EXT_TRAP_PHYTXERR_INFO_VER_V2 2 499 typedef struct hnd_ext_trap_macphytxerr { 500 uint8 version; /* version of the information following this */ 501 uint8 trap_reason; 502 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 503 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 504 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 505 uint16 i16_0x846; /* TDC_FrmLen0 */ 506 uint16 i16_0x848; /* TDC_FrmLen1 */ 507 uint16 i16_0x84a; /* TDC_Txtime */ 508 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 509 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 510 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 511 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 512 uint16 i16_0x490; /* psm_brc */ 513 uint16 i16_0x4d8; /* psm_brc_1 */ 514 uint16 shm_txerr_reason; 515 uint16 shm_pctl0; 516 uint16 shm_pctl1; 517 uint16 shm_pctl2; 518 uint16 shm_lsig0; 519 uint16 shm_lsig1; 520 uint16 shm_plcp0; 521 uint16 shm_plcp1; 522 uint16 shm_plcp2; 523 uint16 shm_vht_sigb0; 524 uint16 shm_vht_sigb1; 525 uint16 shm_tx_tst; 526 uint16 shm_txerr_tm; 527 uint16 shm_curchannel; 528 uint16 shm_crx_rxtsf_pos; 529 uint16 shm_lasttx_tsf; 530 uint16 shm_s_rxtsftmrval; 531 uint16 i16_0x29; /* Phy indirect address */ 532 uint16 i16_0x2a; /* Phy indirect address */ 533 } hnd_ext_trap_macphytxerr_t; 534 535 typedef struct hnd_ext_trap_macphytxerr_v2 { 536 uint8 version; /* version of the information following this */ 537 uint8 trap_reason; 538 uint16 i16_0x63E; /* tsf_tmr_rx_ts */ 539 uint16 i16_0x640; /* tsf_tmr_tx_ts */ 540 uint16 i16_0x642; /* tsf_tmr_rx_end_ts */ 541 uint16 i16_0x846; /* TDC_FrmLen0 */ 542 uint16 i16_0x848; /* TDC_FrmLen1 */ 543 uint16 i16_0x84a; /* TDC_Txtime */ 544 uint16 i16_0xa5a; /* TXE_BytCntInTxFrmLo */ 545 uint16 i16_0xa5c; /* TXE_BytCntInTxFrmHi */ 546 uint16 i16_0x856; /* TDC_VhtPsduLen0 */ 547 uint16 i16_0x858; /* TDC_VhtPsduLen1 */ 548 uint16 i16_0x490; /* psm_brc */ 549 uint16 i16_0x4d8; /* psm_brc_1 */ 550 uint16 shm_txerr_reason; 551 uint16 shm_pctl0; 552 uint16 shm_pctl1; 553 uint16 shm_pctl2; 554 uint16 shm_lsig0; 555 uint16 shm_lsig1; 556 uint16 shm_plcp0; 557 uint16 shm_plcp1; 558 uint16 shm_plcp2; 559 uint16 shm_vht_sigb0; 560 uint16 shm_vht_sigb1; 561 uint16 shm_tx_tst; 562 uint16 shm_txerr_tm; 563 uint16 shm_curchannel; 564 uint16 shm_crx_rxtsf_pos; 565 uint16 shm_lasttx_tsf; 566 uint16 shm_s_rxtsftmrval; 567 uint16 i16_0x29; /* Phy indirect address */ 568 uint16 i16_0x2a; /* Phy indirect address */ 569 uint8 phyerr_bmac_cnt; /* number of times bmac raised phy tx err */ 570 uint8 phyerr_bmac_rsn; /* bmac reason for phy tx error */ 571 uint16 pad; 572 uint32 recv_fifo_status[3][2]; /* Rcv Status0 & Rcv Status1 for 3 Rx fifos */ 573 } hnd_ext_trap_macphytxerr_v2_t; 574 575 #define HND_EXT_TRAP_PCIE_ERR_ATTN_VER_1 (1u) 576 #define MAX_AER_HDR_LOG_REGS (4u) 577 typedef struct hnd_ext_trap_pcie_err_attn_v1 { 578 uint8 version; 579 uint8 pad[3]; 580 uint32 err_hdr_logreg1; 581 uint32 err_hdr_logreg2; 582 uint32 err_hdr_logreg3; 583 uint32 err_hdr_logreg4; 584 uint32 err_code_logreg; 585 uint32 err_type; 586 uint32 err_code_state; 587 uint32 last_err_attn_ts; 588 uint32 cfg_tlp_hdr[MAX_AER_HDR_LOG_REGS]; 589 } hnd_ext_trap_pcie_err_attn_v1_t; 590 591 #define MAX_EVENTLOG_BUFFERS 48 592 typedef struct eventlog_trapdata_info { 593 uint32 num_elements; 594 uint32 seq_num; 595 uint32 log_arr_addr; 596 } eventlog_trapdata_info_t; 597 598 typedef struct eventlog_trap_buf_info { 599 uint32 len; 600 uint32 buf_addr; 601 } eventlog_trap_buf_info_t; 602 603 #if defined(ETD) && !defined(WLETD) 604 #define ETD_SW_FLAG_MEM 0x00000001 605 606 int etd_init(osl_t *osh); 607 int etd_register_trap_ext_callback(void *cb, void *arg); 608 int (etd_register_trap_ext_callback_late)(void *cb, void *arg); 609 uint32 *etd_get_trap_ext_data(void); 610 uint32 etd_get_trap_ext_swflags(void); 611 void etd_set_trap_ext_swflag(uint32 flag); 612 void etd_notify_trap_ext_callback(trap_t *tr); 613 reg_dump_config_t *etd_get_reg_dump_config_tbl(void); 614 uint etd_get_reg_dump_config_len(void); 615 616 extern bool _etd_enab; 617 618 #define ETD_ENAB(pub) (_etd_enab) 619 620 #else 621 #define ETD_ENAB(pub) (0) 622 #endif /* WLETD */ 623 624 #endif /* !LANGUAGE_ASSEMBLY */ 625 626 #endif /* _ETD_H_ */ 627