1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef _RGA_DRIVER_H_ 3 #define _RGA_DRIVER_H_ 4 5 #include <linux/mutex.h> 6 #include <linux/scatterlist.h> 7 #include <linux/dma-buf.h> 8 9 #define RGA_BLIT_SYNC 0x5017 10 #define RGA_BLIT_ASYNC 0x5018 11 #define RGA_FLUSH 0x5019 12 #define RGA_GET_RESULT 0x501a 13 #define RGAGET_VERSION 0x501b 14 #define RGA_CACHE_FLUSH 0x501c 15 16 #define RGA2_BLIT_SYNC 0x6017 17 #define RGA2_BLIT_ASYNC 0x6018 18 #define RGA2_FLUSH 0x6019 19 #define RGA2_GET_RESULT 0x601a 20 #define RGA2GET_VERSION 0x601b 21 22 #define RGA2_REG_CTRL_LEN 0x8 /* 8 */ 23 #define RGA2_REG_CMD_LEN 0x20 /* 32 */ 24 #define RGA2_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 25 26 #define RGA2_OUT_OF_RESOURCES (-10) 27 #define RGA2_MALLOC_ERROR (-11) 28 29 #define SCALE_DOWN_LARGE 1 30 31 #define rgaIS_ERROR(status) ((status) < 0) 32 #define rgaNO_ERROR(status) ((status) >= 0) 33 #define rgaIS_SUCCESS(status) ((status) == 0) 34 35 #define RGA_BUF_GEM_TYPE_MASK 0xC0 36 #define RGA_BUF_GEM_TYPE_DMA 0x80 37 #define RGA2_MAJOR_VERSION_MASK (0xFF000000) 38 #define RGA2_MINOR_VERSION_MASK (0x00F00000) 39 #define RGA2_SVN_VERSION_MASK (0x000FFFFF) 40 41 #define RGA2_INDEX_TW 2 42 #define RGA2_INDEX_TH 3 43 #define RGA2_INDEX_FO 4 44 #define RGA2_INDEX_FI 5 45 #define RGA2_INDEX_SI 6 46 #define RGA2_INDEX_SE 7 47 #define RGA2_INDEX_EI 8 48 #define RGA2_INDEX_NI 9 49 #define RGA2_INDEX_TE 10 50 #define RGA2_INDEX_EIE 11 51 #define RGA2_INDEX_TWE 12 52 #define RGA2_INDEX_FIF 15 53 #define RGA2_INDEX_SIX 16 54 #define RGA2_INDEX_TWEN 20 55 #define RGA2_INDEX_TWEF 24 56 #define RGA2_INDEX_THIO 31 57 #define RGA2_INDEX_BLOCK 2048 58 #define RGA2_INDEX_SIZE 65536 59 60 /* RGA2 process mode enum */ 61 enum { 62 bitblt_mode = 0x0, 63 color_palette_mode = 0x1, 64 color_fill_mode = 0x2, 65 update_palette_table_mode = 0x3, 66 update_patten_buff_mode = 0x4, 67 }; /* render mode */ 68 69 enum { 70 A_B_B = 0x0, 71 A_B_C = 0x1, 72 }; // bitblt_mode select 73 74 enum { 75 rop_enable_mask = 0x2, 76 dither_enable_mask = 0x8, 77 fading_enable_mask = 0x10, 78 PD_enbale_mask = 0x20, 79 }; 80 81 /* 82 // Alpha Red Green Blue 83 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 84 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 85 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 86 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 87 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 88 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 89 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 90 { 2, 16, {{ 0, 0, 5, 0 11, 5, 16,11}}, GGL_BGR }, // RK_FORMAT_BGR_565 91 { 2, 16, {{ 1, 0, 6, 1, 11, 6, 16,11}}, GGL_BGRA }, // RK_FORMAT_BGRA_5551 92 { 2, 16, {{ 4, 0, 8, 4, 12, 8, 16,12}}, GGL_BGRA }, // RK_FORMAT_BGRA_4444 93 94 */ 95 enum { 96 RGA2_FORMAT_RGBA_8888 = 0x0, 97 RGA2_FORMAT_RGBX_8888 = 0x1, 98 RGA2_FORMAT_RGB_888 = 0x2, 99 RGA2_FORMAT_BGRA_8888 = 0x3, 100 RGA2_FORMAT_BGRX_8888 = 0x4, 101 RGA2_FORMAT_BGR_888 = 0x5, 102 RGA2_FORMAT_RGB_565 = 0x6, 103 RGA2_FORMAT_RGBA_5551 = 0x7, 104 RGA2_FORMAT_RGBA_4444 = 0x8, 105 RGA2_FORMAT_BGR_565 = 0x9, 106 RGA2_FORMAT_BGRA_5551 = 0xa, 107 RGA2_FORMAT_BGRA_4444 = 0xb, 108 109 RGA2_FORMAT_Y4 = 0xe, 110 RGA2_FORMAT_YCbCr_400 = 0xf, 111 112 RGA2_FORMAT_YCbCr_422_SP = 0x10, 113 RGA2_FORMAT_YCbCr_422_P = 0x11, 114 RGA2_FORMAT_YCbCr_420_SP = 0x12, 115 RGA2_FORMAT_YCbCr_420_P = 0x13, 116 RGA2_FORMAT_YCrCb_422_SP = 0x14, 117 RGA2_FORMAT_YCrCb_422_P = 0x15, 118 RGA2_FORMAT_YCrCb_420_SP = 0x16, 119 RGA2_FORMAT_YCrCb_420_P = 0x17, 120 121 RGA2_FORMAT_YVYU_422 = 0x18, 122 RGA2_FORMAT_YVYU_420 = 0x19, 123 RGA2_FORMAT_VYUY_422 = 0x1a, 124 RGA2_FORMAT_VYUY_420 = 0x1b, 125 RGA2_FORMAT_YUYV_422 = 0x1c, 126 RGA2_FORMAT_YUYV_420 = 0x1d, 127 RGA2_FORMAT_UYVY_422 = 0x1e, 128 RGA2_FORMAT_UYVY_420 = 0x1f, 129 130 RGA2_FORMAT_YCbCr_420_SP_10B = 0x20, 131 RGA2_FORMAT_YCrCb_420_SP_10B = 0x21, 132 RGA2_FORMAT_YCbCr_422_SP_10B = 0x22, 133 RGA2_FORMAT_YCrCb_422_SP_10B = 0x23, 134 135 RGA2_FORMAT_BPP_1 = 0x24, 136 RGA2_FORMAT_BPP_2 = 0x25, 137 RGA2_FORMAT_BPP_4 = 0x26, 138 RGA2_FORMAT_BPP_8 = 0x27, 139 140 RGA2_FORMAT_ARGB_8888 = 0x28, 141 RGA2_FORMAT_XRGB_8888 = 0x29, 142 RGA2_FORMAT_ARGB_5551 = 0x2a, 143 RGA2_FORMAT_ARGB_4444 = 0x2b, 144 RGA2_FORMAT_ABGR_8888 = 0x2c, 145 RGA2_FORMAT_XBGR_8888 = 0x2d, 146 RGA2_FORMAT_ABGR_5551 = 0x2e, 147 RGA2_FORMAT_ABGR_4444 = 0x2f, 148 }; 149 150 typedef struct mdp_img { 151 u16 width; 152 u16 height; 153 u32 format; 154 u32 mem_addr; 155 } mdp_img; 156 157 typedef struct mdp_img_act { 158 u16 width; // width 159 u16 height; // height 160 s16 x_off; // x offset for the vir 161 s16 y_off; // y offset for the vir 162 s16 uv_x_off; 163 s16 uv_y_off; 164 } mdp_img_act; 165 166 typedef struct mdp_img_vir { 167 u16 width; 168 u16 height; 169 u32 format; 170 u32 mem_addr; 171 u32 uv_addr; 172 u32 v_addr; 173 } mdp_img_vir; 174 175 typedef struct MMU_INFO { 176 unsigned long src0_base_addr; 177 unsigned long src1_base_addr; 178 unsigned long dst_base_addr; 179 unsigned long els_base_addr; 180 181 u8 src0_mmu_flag; /* [0] src0 mmu enable [1] src0_flush [2] src0_prefetch_en [3] src0_prefetch dir */ 182 u8 src1_mmu_flag; /* [0] src1 mmu enable [1] src1_flush [2] src1_prefetch_en [3] src1_prefetch dir */ 183 u8 dst_mmu_flag; /* [0] dst mmu enable [1] dst_flush [2] dst_prefetch_en [3] dst_prefetch dir */ 184 u8 els_mmu_flag; /* [0] els mmu enable [1] els_flush [2] els_prefetch_en [3] els_prefetch dir */ 185 } MMU_INFO; 186 187 enum { MMU_DIS = 0x0, MMU_EN = 0x1 }; 188 enum { MMU_FLUSH_DIS = 0x0, MMU_FLUSH_EN = 0x2 }; 189 enum { MMU_PRE_DIS = 0x0, MMU_PRE_EN = 0x4 }; 190 enum { MMU_PRE_DIR_FORW = 0x0, MMU_PRE_DIR_BACK = 0x8 }; 191 typedef struct COLOR_FILL { 192 s16 gr_x_a; 193 s16 gr_y_a; 194 s16 gr_x_b; 195 s16 gr_y_b; 196 s16 gr_x_g; 197 s16 gr_y_g; 198 s16 gr_x_r; 199 s16 gr_y_r; 200 } COLOR_FILL; 201 202 enum { ALPHA_ORIGINAL = 0x0, ALPHA_NO_128 = 0x1 }; 203 204 enum { 205 R2_BLACK = 0x00, 206 R2_COPYPEN = 0xf0, 207 R2_MASKNOTPEN = 0x0a, 208 R2_MASKPEN = 0xa0, 209 R2_MASKPENNOT = 0x50, 210 R2_MERGENOTPEN = 0xaf, 211 R2_MERGEPEN = 0xfa, 212 R2_MERGEPENNOT = 0xf5, 213 R2_NOP = 0xaa, 214 R2_NOT = 0x55, 215 R2_NOTCOPYPEN = 0x0f, 216 R2_NOTMASKPEN = 0x5f, 217 R2_NOTMERGEPEN = 0x05, 218 R2_NOTXORPEN = 0xa5, 219 R2_WHITE = 0xff, 220 R2_XORPEN = 0x5a 221 }; 222 223 /***************************************/ 224 /* porting from rga.h for msg convert */ 225 /***************************************/ 226 227 typedef struct FADING { 228 uint8_t b; 229 uint8_t g; 230 uint8_t r; 231 uint8_t res; 232 } FADING; 233 234 typedef struct MMU { 235 unsigned char mmu_en; 236 unsigned long base_addr; 237 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size */ 238 } MMU; 239 240 typedef struct MMU_32 { 241 unsigned char mmu_en; 242 uint32_t base_addr; 243 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size */ 244 } MMU_32; 245 246 typedef struct RECT { 247 unsigned short xmin; 248 unsigned short xmax; // width - 1 249 unsigned short ymin; 250 unsigned short ymax; // height - 1 251 } RECT; 252 253 typedef struct POINT { 254 unsigned short x; 255 unsigned short y; 256 } POINT; 257 258 typedef struct line_draw_t { 259 POINT start_point; /* LineDraw_start_point */ 260 POINT end_point; /* LineDraw_end_point */ 261 uint32_t color; /* LineDraw_color */ 262 uint32_t flag; /* (enum) LineDrawing mode sel */ 263 uint32_t line_width; /* range 1~16 */ 264 } line_draw_t; 265 266 /* color space convert coefficient. */ 267 typedef struct csc_coe_t { 268 int16_t r_v; 269 int16_t g_y; 270 int16_t b_u; 271 int32_t off; 272 } csc_coe_t; 273 274 typedef struct full_csc_t { 275 unsigned char flag; 276 csc_coe_t coe_y; 277 csc_coe_t coe_u; 278 csc_coe_t coe_v; 279 } full_csc_t; 280 281 typedef struct rga_img_info_t { 282 unsigned long yrgb_addr; /* yrgb mem addr */ 283 unsigned long uv_addr; /* cb/cr mem addr */ 284 unsigned long v_addr; /* cr mem addr */ 285 unsigned int format; // definition by RK_FORMAT 286 287 unsigned short act_w; 288 unsigned short act_h; 289 unsigned short x_offset; 290 unsigned short y_offset; 291 292 unsigned short vir_w; 293 unsigned short vir_h; 294 295 unsigned short endian_mode; // for BPP 296 unsigned short alpha_swap; /* not use */ 297 } rga_img_info_t; 298 299 typedef struct rga_img_info_32_t { 300 uint32_t yrgb_addr; /* yrgb mem addr */ 301 uint32_t uv_addr; /* cb/cr mem addr */ 302 uint32_t v_addr; /* cr mem addr */ 303 unsigned int format; // definition by RK_FORMAT 304 unsigned short act_w; 305 unsigned short act_h; 306 unsigned short x_offset; 307 unsigned short y_offset; 308 unsigned short vir_w; 309 unsigned short vir_h; 310 unsigned short endian_mode; // for BPP 311 unsigned short alpha_swap; 312 } rga_img_info_32_t; 313 314 struct rga_dma_buffer_t { 315 /* DMABUF information */ 316 struct dma_buf *dma_buf; 317 struct dma_buf_attachment *attach; 318 struct sg_table *sgt; 319 320 dma_addr_t iova; 321 unsigned long size; 322 void *vaddr; 323 enum dma_data_direction dir; 324 }; 325 326 struct rga_req { 327 uint8_t render_mode; /* (enum) process mode sel */ 328 329 rga_img_info_t src; /* src image info */ 330 rga_img_info_t dst; /* dst image info */ 331 rga_img_info_t pat; /* patten image info */ 332 333 unsigned long rop_mask_addr; /* rop4 mask addr */ 334 unsigned long LUT_addr; /* LUT addr */ 335 336 RECT clip; /* dst clip window default value is dst_vir */ 337 /* value from [0, w-1] / [0, h-1] */ 338 339 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 340 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 341 342 uint16_t alpha_rop_flag; /* alpha rop process flag */ 343 /* ([0] = 1 alpha_rop_enable) */ 344 /* ([1] = 1 rop enable) */ 345 /* ([2] = 1 fading_enable) */ 346 /* ([3] = 1 PD_enable) */ 347 /* ([4] = 1 alpha cal_mode_sel) */ 348 /* ([5] = 1 dither_enable) */ 349 /* ([6] = 1 gradient fill mode sel) */ 350 /* ([7] = 1 AA_enable) */ 351 352 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 353 354 uint32_t color_key_max; /* color key max */ 355 uint32_t color_key_min; /* color key min */ 356 357 uint32_t fg_color; /* foreground color */ 358 uint32_t bg_color; /* background color */ 359 360 COLOR_FILL gr_color; /* color fill use gradient */ 361 362 line_draw_t line_draw_info; 363 364 FADING fading; 365 366 uint8_t PD_mode; /* porter duff alpha mode sel */ 367 368 uint8_t alpha_global_value; /* global alpha value */ 369 370 uint16_t rop_code; /* rop2/3/4 code scan from rop code table */ 371 372 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type */ 373 374 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp */ 375 376 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 377 378 uint8_t endian_mode; /* 0/big endian 1/little endian */ 379 380 uint8_t rotate_mode; /* (enum) rotate mode */ 381 /* 0x0, no rotate */ 382 /* 0x1, rotate */ 383 /* 0x2, x_mirror */ 384 /* 0x3, y_mirror */ 385 386 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 387 388 MMU mmu_info; /* mmu information */ 389 390 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 391 /* ([2~3] rop mode) */ 392 /* ([4] zero mode en) */ 393 /* ([5] dst alpha mode) */ 394 /* ([6] alpha output mode sel) 0 src / 1 dst */ 395 396 uint8_t src_trans_mode; 397 398 uint8_t dither_mode; 399 400 full_csc_t full_csc; /* full color space convert */ 401 }; 402 struct rga_req_32 { 403 uint8_t render_mode; /* (enum) process mode sel */ 404 rga_img_info_32_t src; /* src image info */ 405 rga_img_info_32_t dst; /* dst image info */ 406 rga_img_info_32_t pat; /* patten image info */ 407 uint32_t rop_mask_addr; /* rop4 mask addr */ 408 uint32_t LUT_addr; /* LUT addr */ 409 RECT clip; /* dst clip window default value is dst_vir */ 410 /* value from [0, w-1] / [0, h-1] */ 411 int32_t sina; /* dst angle default value 0 16.16 scan from table */ 412 int32_t cosa; /* dst angle default value 0 16.16 scan from table */ 413 uint16_t alpha_rop_flag; /* alpha rop process flag */ 414 /* ([0] = 1 alpha_rop_enable) */ 415 /* ([1] = 1 rop enable) */ 416 /* ([2] = 1 fading_enable) */ 417 /* ([3] = 1 PD_enable) */ 418 /* ([4] = 1 alpha cal_mode_sel) */ 419 /* ([5] = 1 dither_enable) */ 420 /* ([6] = 1 gradient fill mode sel) */ 421 /* ([7] = 1 AA_enable) */ 422 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 423 uint32_t color_key_max; /* color key max */ 424 uint32_t color_key_min; /* color key min */ 425 uint32_t fg_color; /* foreground color */ 426 uint32_t bg_color; /* background color */ 427 COLOR_FILL gr_color; /* color fill use gradient */ 428 line_draw_t line_draw_info; 429 FADING fading; 430 uint8_t PD_mode; /* porter duff alpha mode sel */ 431 uint8_t alpha_global_value; /* global alpha value */ 432 uint16_t rop_code; /* rop2/3/4 code scan from rop code table */ 433 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type */ 434 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp */ 435 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 436 uint8_t endian_mode; /* 0/big endian 1/little endian */ 437 uint8_t rotate_mode; /* (enum) rotate mode */ 438 /* 0x0, no rotate */ 439 /* 0x1, rotate */ 440 /* 0x2, x_mirror */ 441 /* 0x3, y_mirror */ 442 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */ 443 MMU_32 mmu_info; /* mmu information */ 444 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */ 445 /* ([2~3] rop mode) */ 446 /* ([4] zero mode en) */ 447 /* ([5] dst alpha mode) */ 448 /* ([6] alpha output mode sel) 0 src / 1 dst */ 449 uint8_t src_trans_mode; 450 451 uint8_t dither_mode; 452 453 full_csc_t full_csc; /* full color space convert */ 454 }; 455 456 struct rga2_req { 457 u8 render_mode; /* (enum) process mode sel */ 458 459 rga_img_info_t src; // src active window 460 rga_img_info_t src1; // src1 active window 461 rga_img_info_t dst; // dst active window 462 rga_img_info_t pat; // patten active window 463 464 unsigned long rop_mask_addr; // rop4 mask addr 465 unsigned long LUT_addr; // LUT addr 466 467 u32 rop_mask_stride; 468 469 u8 bitblt_mode; /* 0: SRC + DST => DST */ 470 /* 1: SRC + SRC1 => DST */ 471 472 u8 rotate_mode; /* [1:0] */ 473 /* 0 degree 0x0 */ 474 /* 90 degree 0x1 */ 475 /* 180 degree 0x2 */ 476 /* 270 degree 0x3 */ 477 /* [5:4] */ 478 /* none 0x0 */ 479 /* x_mirror 0x1 */ 480 /* y_mirror 0x2 */ 481 /* x_mirror + y_mirror 0x3 */ 482 483 u16 alpha_rop_flag; /* alpha rop process flag */ 484 /* ([0] = 1 alpha_rop_enable) */ 485 /* ([1] = 1 rop enable) */ 486 /* ([2] = 1 fading_enable) */ 487 /* ([3] = 1 alpha cal_mode_sel) */ 488 /* ([4] = 1 src_dither_up_enable) */ 489 /* ([5] = 1 dst_dither_up_enable) */ 490 /* ([6] = 1 dither_down_enable) */ 491 /* ([7] = 1 gradient fill mode sel) */ 492 493 u16 alpha_mode_0; /* [0] SrcAlphaMode0 */ 494 /* [2:1] SrcGlobalAlphaMode0 */ 495 /* [3] SrcAlphaSelectMode0 */ 496 /* [6:4] SrcFactorMode0 */ 497 /* [7] SrcColorMode */ 498 499 /* [8] DstAlphaMode0 */ 500 /* [10:9] DstGlobalAlphaMode0 */ 501 /* [11] DstAlphaSelectMode0 */ 502 /* [14:12] DstFactorMode0 */ 503 /* [15] DstColorMode0 */ 504 505 u16 alpha_mode_1; /* [0] SrcAlphaMode1 */ 506 /* [2:1] SrcGlobalAlphaMode1 */ 507 /* [3] SrcAlphaSelectMode1 */ 508 /* [6:4] SrcFactorMode1 */ 509 510 /* [8] DstAlphaMode1 */ 511 /* [10:9] DstGlobalAlphaMode1 */ 512 /* [11] DstAlphaSelectMode1 */ 513 /* [14:12] DstFactorMode1 */ 514 515 u8 scale_bicu_mode; /* 0 1 2 3 */ 516 517 u32 color_key_max; /* color key max */ 518 u32 color_key_min; /* color key min */ 519 520 u32 fg_color; /* foreground color */ 521 u32 bg_color; /* background color */ 522 523 u8 color_fill_mode; 524 COLOR_FILL gr_color; /* color fill use gradient */ 525 526 u8 fading_alpha_value; /* Fading value */ 527 u8 fading_r_value; 528 u8 fading_g_value; 529 u8 fading_b_value; 530 531 u8 src_a_global_val; /* src global alpha value */ 532 u8 dst_a_global_val; /* dst global alpha value */ 533 534 u8 rop_mode; /* rop mode select 0 : rop2 1 : rop3 2 : rop4 */ 535 u16 rop_code; /* rop2/3/4 code */ 536 537 u8 palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp */ 538 539 u8 yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 540 /* [1:0] src0 csc mode */ 541 /* [3:2] dst csc mode */ 542 /* [4] dst csc clip enable */ 543 /* [6:5] src1 csc mdoe */ 544 /* [7] src1 csc clip enable */ 545 full_csc_t full_csc; /* full color space convert */ 546 547 u8 endian_mode; /* 0/little endian 1/big endian */ 548 549 u8 CMD_fin_int_enable; 550 551 MMU_INFO mmu_info; /* mmu infomation */ 552 553 u8 alpha_zero_key; 554 u8 src_trans_mode; 555 556 u8 alpha_swp; /* not use */ 557 u8 dither_mode; 558 559 u8 rgb2yuv_mode; 560 561 u8 buf_type; 562 }; 563 564 struct rga2_mmu_buf_t { 565 int32_t front; 566 int32_t back; 567 int32_t size; 568 int32_t curr; 569 unsigned int *buf; 570 unsigned int *buf_virtual; 571 572 struct page **pages; 573 574 u8 buf_order; 575 u8 pages_order; 576 }; 577 578 enum { 579 BB_ROTATE_OFF = 0x0, /* no rotate */ 580 BB_ROTATE_90 = 0x1, /* rotate 90 */ 581 BB_ROTATE_180 = 0x2, /* rotate 180 */ 582 BB_ROTATE_270 = 0x3, /* rotate 270 */ 583 }; /* rotate mode */ 584 585 enum { 586 BB_MIRROR_OFF = (0x0 << 4), /* no mirror */ 587 BB_MIRROR_X = (0x1 << 4), /* x mirror */ 588 BB_MIRROR_Y = (0x2 << 4), /* y mirror */ 589 BB_MIRROR_XY = (0x3 << 4), /* xy mirror */ 590 }; /* mirror mode */ 591 592 enum { 593 BB_COPY_USE_TILE = (0x1 << 6), /* bitblt mode copy but use Tile mode */ 594 }; 595 596 enum { 597 // BYPASS = 0x0, 598 BT_601_RANGE0 = 0x1, 599 BT_601_RANGE1 = 0x2, 600 BT_709_RANGE0 = 0x3, 601 }; /* yuv2rgb_mode */ 602 603 enum { 604 BPP1 = 0x0, /* BPP1 */ 605 BPP2 = 0x1, /* BPP2 */ 606 BPP4 = 0x2, /* BPP4 */ 607 BPP8 = 0x3 /* BPP8 */ 608 }; /* palette_mode */ 609 610 enum { 611 SOLID_COLOR = 0x0, // color fill mode; ROP4: SOLID_rop4_mask_addr COLOR 612 PATTERN_COLOR = 0x1 // pattern_fill_mode;ROP4:PATTERN_COLOR 613 }; /* color fill mode */ 614 615 enum { COLOR_FILL_CLIP = 0x0, COLOR_FILL_NOT_CLIP = 0x1 }; 616 617 enum { 618 CATROM = 0x0, 619 MITCHELL = 0x1, 620 HERMITE = 0x2, 621 B_SPLINE = 0x3, 622 }; /* bicubic coefficient */ 623 624 enum { ROP2 = 0x0, ROP3 = 0x1, ROP4 = 0x2 }; /* ROP mode */ 625 626 enum { BIG_ENDIAN = 0x0, LITTLE_ENDIAN = 0x1 }; /* endian mode */ 627 628 enum { 629 MMU_TABLE_4KB = 0x0, 630 MMU_TABLE_64KB = 0x1, 631 }; /* MMU table size */ 632 633 enum { 634 RGB_2_666 = 0x0, 635 RGB_2_565 = 0x1, 636 RGB_2_555 = 0x2, 637 RGB_2_444 = 0x3, 638 }; /* dither down mode */ 639 640 /** 641 * struct for process session which connect to rga 642 * 643 * @author ZhangShengqin (2012-2-15) 644 */ 645 typedef struct rga2_session { 646 /* a linked list of data so we can access them for debugging */ 647 struct list_head list_session; 648 /* a linked list of register data waiting for process */ 649 struct list_head waiting; 650 /* a linked list of register data in processing */ 651 struct list_head running; 652 /* all coommand this thread done */ 653 atomic_t done; 654 wait_queue_head_t wait; 655 pid_t pid; 656 atomic_t task_running; 657 atomic_t num_done; 658 } rga2_session; 659 660 struct rga2_reg { 661 rga2_session *session; 662 struct list_head session_link; 663 struct list_head status_link; 664 uint32_t sys_reg[8]; 665 uint32_t csc_reg[12]; 666 uint32_t cmd_reg[32]; 667 668 uint32_t *MMU_src0_base; 669 uint32_t *MMU_src1_base; 670 uint32_t *MMU_dst_base; 671 uint32_t MMU_src0_count; 672 uint32_t MMU_src1_count; 673 uint32_t MMU_dst_count; 674 675 uint32_t MMU_len; 676 bool MMU_map; 677 678 struct rga_dma_buffer_t dma_buffer_src0; 679 struct rga_dma_buffer_t dma_buffer_src1; 680 struct rga_dma_buffer_t dma_buffer_dst; 681 struct rga_dma_buffer_t dma_buffer_els; 682 }; 683 684 struct rga2_service_info { 685 struct mutex lock; 686 struct timer_list timer; /* timer for power off */ 687 struct list_head waiting; /* link to link_reg in struct vpu_reg */ 688 struct list_head running; /* link to link_reg in struct vpu_reg */ 689 struct list_head done; /* link to link_reg in struct vpu_reg */ 690 struct list_head session; /* link to list_session in struct vpu_session */ 691 atomic_t total_running; 692 693 struct rga2_reg *reg; 694 695 uint32_t cmd_buff[32 * 8]; /* cmd_buff for rga */ 696 uint32_t *pre_scale_buf; 697 atomic_t int_disable; /* 0 int enable 1 int disable */ 698 atomic_t cmd_num; 699 atomic_t src_format_swt; 700 int last_prc_src_format; 701 atomic_t rga_working; 702 bool enable; 703 uint32_t dev_mode; 704 705 struct mutex mutex; // mutex 706 }; 707 708 #define RGA2_TEST_CASE 0 709 710 // General Registers 711 #define RGA2_SYS_CTRL 0x000 712 #define RGA2_CMD_CTRL 0x004 713 #define RGA2_CMD_BASE 0x008 714 #define RGA2_STATUS 0x00c 715 #define RGA2_INT 0x010 716 #define RGA2_MMU_CTRL0 0x018 717 #define RGA2_MMU_CMD_BASE 0x01c 718 719 // Full Csc Coefficient 720 #define RGA2_CSC_COE_BASE 0x60 721 722 // Command code start 723 #define RGA2_MODE_CTRL 0x100 724 #define RGA_BLIT_COMPLETE_EVENT 1 725 726 #endif /* _RK29_IPP_DRIVER_H_ */ 727