1 /**
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 *
15 * Description: Provides i2s port \n
16 *
17 * History: \n
18 * 2023-03-10， Create file. \n
19 */
20
21 #include "common_def.h"
22 #include "hal_sio_v151.h"
23 #include "oal_interface.h"
24 #include "soc_osal.h"
25 #include "pinctrl_porting.h"
26 #include "pinctrl.h"
27 #include "chip_core_irq.h"
28 #include "sio_porting.h"
29 #if defined(CONFIG_I2S_SUPPORT_DMA)
30 #include "dma_porting.h"
31 #endif
32 #include "debug_print.h"
33
34 #define FREQ_OD_NEED 32
35 #define I2S_MCLK_DIV 2
36 #define I2S_MCLK_RATE 12288
37 #define I2S_BUS_0_REAL_BASE (I2S_BUS_0_BASE_ADDR - 0x3c)
38 #define I2S_MERGE_TX_DATA_ADDR (I2S_BUS_0_REAL_BASE + 0xc0)
39 #define I2S_MERGE_RX_DATA_ADDR (I2S_BUS_0_REAL_BASE + 0xa0)
40 #define I2S_TX_SPLIT_LEFT_DATA_ADDR (I2S_BUS_0_REAL_BASE + 0x4c)
41 #define I2S_TX_SPLIT_RIGHT_DATA_ADDR (I2S_BUS_0_REAL_BASE + 0x50)
42 #define I2S_RX_SPLIT_LEFT_DATA_ADDR (I2S_BUS_0_REAL_BASE + 0x54)
43 #define I2S_RX_SPLIT_RIGHT_DATA_ADDR (I2S_BUS_0_REAL_BASE + 0x58)
44 #define HAL_I2S_CLK_CG_ADDR 0x44001100
45 #define CMU_NEW_CFG0 0x400034a0
46 #define HAL_I2S_CLK_CG_ON 0xffffffff
47 #define I2S_CLKEN_BIT 12
48 #define I2S_BUS_CLKEN_BIT 11
49 #define CMU_DIV_AD_RSTN_SYNC_BIT 0
50
51 static uintptr_t g_sio_base_addrs[I2S_MAX_NUMBER] = {
52 (uintptr_t)I2S_BUS_0_BASE_ADDR,
53 };
54
55 typedef struct sio_interrupt {
56 core_irq_t irq_num;
57 osal_irq_handler irq_func;
58 }sio_interrupt_t;
59
60 static const sio_interrupt_t g_sio_interrupt_lines[I2S_MAX_NUMBER] = {
61 { I2S_IRQN, (osal_irq_handler)irq_sio0_handler },
62 };
63
sio_porting_base_addr_get(sio_bus_t bus)64 uintptr_t sio_porting_base_addr_get(sio_bus_t bus)
65 {
66 return g_sio_base_addrs[bus];
67 }
68
sio_porting_register_hal_funcs(sio_bus_t bus)69 void sio_porting_register_hal_funcs(sio_bus_t bus)
70 {
71 hal_sio_register_funcs(bus, hal_sio_v151_funcs_get());
72 }
73
sio_porting_unregister_hal_funcs(sio_bus_t bus)74 void sio_porting_unregister_hal_funcs(sio_bus_t bus)
75 {
76 hal_sio_unregister_funcs(bus);
77 }
78
sio_porting_register_irq(sio_bus_t bus)79 void sio_porting_register_irq(sio_bus_t bus)
80 {
81 osal_irq_request(g_sio_interrupt_lines[bus].irq_num, g_sio_interrupt_lines[bus].irq_func, NULL, NULL, NULL);
82 osal_irq_enable(g_sio_interrupt_lines[bus].irq_num);
83 }
84
sio_porting_unregister_irq(sio_bus_t bus)85 void sio_porting_unregister_irq(sio_bus_t bus)
86 {
87 osal_irq_disable(g_sio_interrupt_lines[bus].irq_num);
88 }
89
irq_sio0_handler(void)90 void irq_sio0_handler(void)
91 {
92 hal_sio_v151_irq_handler(SIO_BUS_0);
93 }
94
sio_porting_clock_enable(bool enable)95 void sio_porting_clock_enable(bool enable)
96 {
97 if (enable) {
98 uapi_reg_setbit(CMU_NEW_CFG0, CMU_DIV_AD_RSTN_SYNC_BIT);
99 uapi_reg_setbit(HAL_I2S_CLK_CG_ADDR, I2S_CLKEN_BIT);
100 uapi_reg_setbit(HAL_I2S_CLK_CG_ADDR, I2S_BUS_CLKEN_BIT);
101 } else {
102 uapi_reg_clrbit(CMU_NEW_CFG0, CMU_DIV_AD_RSTN_SYNC_BIT);
103 uapi_reg_clrbit(HAL_I2S_CLK_CG_ADDR, I2S_CLKEN_BIT);
104 uapi_reg_clrbit(HAL_I2S_CLK_CG_ADDR, I2S_BUS_CLKEN_BIT);
105 }
106 }
107
sio_porting_i2s_pinmux(void)108 void sio_porting_i2s_pinmux(void)
109 {
110 uapi_pin_set_mode(S_MGPIO9, PIN_MODE_4);
111 uapi_pin_set_mode(S_MGPIO10, PIN_MODE_4);
112 uapi_pin_set_mode(S_MGPIO11, PIN_MODE_4);
113 uapi_pin_set_mode(S_MGPIO12, PIN_MODE_4);
114 return;
115 }
116
i2s_porting_tx_merge_data_addr_get(sio_bus_t bus)117 uintptr_t i2s_porting_tx_merge_data_addr_get(sio_bus_t bus)
118 {
119 unused(bus);
120 return I2S_MERGE_TX_DATA_ADDR;
121 }
122
i2s_porting_rx_merge_data_addr_get(sio_bus_t bus)123 uintptr_t i2s_porting_rx_merge_data_addr_get(sio_bus_t bus)
124 {
125 unused(bus);
126 return I2S_MERGE_RX_DATA_ADDR;
127 }
128
i2s_porting_tx_left_data_addr_get(sio_bus_t bus)129 uintptr_t i2s_porting_tx_left_data_addr_get(sio_bus_t bus)
130 {
131 unused(bus);
132 return I2S_TX_SPLIT_LEFT_DATA_ADDR;
133 }
134
i2s_porting_tx_right_data_addr_get(sio_bus_t bus)135 uintptr_t i2s_porting_tx_right_data_addr_get(sio_bus_t bus)
136 {
137 unused(bus);
138 return I2S_TX_SPLIT_RIGHT_DATA_ADDR;
139 }
140
i2s_porting_rx_left_data_addr_get(sio_bus_t bus)141 uintptr_t i2s_porting_rx_left_data_addr_get(sio_bus_t bus)
142 {
143 unused(bus);
144 return I2S_RX_SPLIT_LEFT_DATA_ADDR;
145 }
146
i2s_porting_rx_right_data_addr_get(sio_bus_t bus)147 uintptr_t i2s_porting_rx_right_data_addr_get(sio_bus_t bus)
148 {
149 unused(bus);
150 return I2S_RX_SPLIT_RIGHT_DATA_ADDR;
151 }
152
sio_porting_get_bclk_div_num(uint8_t data_width,uint32_t ch)153 uint32_t sio_porting_get_bclk_div_num(uint8_t data_width, uint32_t ch)
154 {
155 uint32_t s_clk, bclk_div_num, freq_of_need;
156 float middle_div;
157 s_clk = I2S_MCLK_RATE;
158 freq_of_need = FREQ_OF_NEED;
159 middle_div = s_clk / (freq_of_need * data_width * ch);
160 if ((uint32_t)(middle_div * I2S_PARAM + 1) == ((uint32_t)middle_div * I2S_PARAM + 1)) {
161 bclk_div_num = (uint32_t)middle_div;
162 } else {
163 bclk_div_num = (uint32_t)middle_div + 1;
164 }
165 return bclk_div_num;
166 }
167
168 #if defined(CONFIG_I2S_SUPPORT_DMA)
i2s_port_get_dma_trans_src_handshaking(sio_bus_t bus)169 uint32_t i2s_port_get_dma_trans_src_handshaking(sio_bus_t bus)
170 {
171 unused(bus);
172 return HAL_DMA_HANDSHAKING_I2S_RX;
173 }
174
i2s_port_get_dma_trans_dest_handshaking(sio_bus_t bus)175 uint32_t i2s_port_get_dma_trans_dest_handshaking(sio_bus_t bus)
176 {
177 unused(bus);
178 return HAL_DMA_HANDSHAKING_I2S_TX;
179 }
180 #endif
181
sio_porting_get_mclk(void)182 uint32_t sio_porting_get_mclk(void)
183 {
184 return I2S_MCLK_RATE;
185 }