1 /** 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * Description: Provides v151 sio register \n 16 * 17 * History: \n 18 * 2023-03-07, Create file. \n 19 */ 20 #ifndef HAL_SIO_V151_REGS_DEF_H 21 #define HAL_SIO_V151_REGS_DEF_H 22 23 #include <stdint.h> 24 25 #ifdef __cplusplus 26 #if __cplusplus 27 extern "C" { 28 #endif /* __cplusplus */ 29 #endif /* __cplusplus */ 30 31 /** 32 * @defgroup drivers_hal_sio_v151_regs_def SIO V151 Regs Definition 33 * @ingroup drivers_hal_sio 34 * @{ 35 */ 36 37 /** 38 * @brief This union represents the bit fields in the sio_version register. 39 * Read the register into the <i>d32</i> member then 40 * set/clear the bits using the <i>b</i> elements. 41 */ 42 typedef union sio_v151_version_data { 43 uint32_t d32; /*!< Raw register data. */ 44 struct { 45 uint32_t version : 8; /*!< sio_version. */ 46 uint32_t loop : 1; /*!< This bit indicates whether enter loop mode or not. 47 0: standard mode. 48 1: loop mode. */ 49 uint32_t reserved9_31 : 23; /*!< Reserved. */ 50 } b; /*!< Register bits. */ 51 } sio_v151_version_data_t; 52 53 /** 54 * @brief This union represents the bit fields in the sio_mode register. 55 * Read the register into the <i>d32</i> member then 56 * set/clear the bits using the <i>b</i> elements. 57 */ 58 typedef union sio_v151_mode_data { 59 uint32_t d32; /*!< Raw register data. */ 60 struct { 61 uint32_t mode : 1; /*!< sio mode. 62 0: i2s mode. 63 1: pcm mode. */ 64 uint32_t pcm_mode : 1; /*!< This bit indicates pcm time mode. 65 0: i2s mode. 66 1: self-defined mode. */ 67 uint32_t rxws_select : 1; /*!< select rx mode ws. */ 68 uint32_t ext_rec_en : 1; /*!< This bit indicates sio mode. 69 0: standard receive mode. 70 1: multi-channel receive mode. */ 71 uint32_t chn_num : 2; /*!< This bit indicates receive channel. 72 00: 2 channel. 73 01: 4 channel. 74 10: 8 channel. 75 11: 16 channel */ 76 uint32_t clk_edge : 1; /*!< This bit indicates clock edge. 77 0: rising edge. 78 1: descending edge. */ 79 uint32_t cfg_i2s_ms_mode_sel : 1; /*!< SIO mode is master/slave. */ 80 uint32_t reserved8_31 : 22; /*!< Reserved. */ 81 } b; /*!< Register bits. */ 82 } sio_v151_mode_data_t; 83 84 /** 85 * @brief This union represents the bit fields in the sio_intstatus register. 86 * Read the register into the <i>d32</i> member then 87 * set/clear the bits using the <i>b</i> elements. 88 */ 89 typedef union sio_v151_intstatus_data { 90 uint32_t d32; /*!< Raw register data. */ 91 struct { 92 uint32_t rx_intr : 1; /*!< The interrupt when rx fifo above threshold. */ 93 uint32_t tx_intr : 1; /*!< The interrupt when tx fifo above threshold. */ 94 uint32_t rx_right_fifo_over : 1; /*!< The interrupt when right tx fifo overflow. */ 95 uint32_t rx_left_fifo_over : 1; /*!< The interrupt when left tx fifo overflow. */ 96 uint32_t tx_right_fifo_under : 1; /*!< The interrupt when right tx fifo underflow. */ 97 uint32_t tx_left_fifo_under : 1; /*!< The interrupt when left tx fifo underflow. */ 98 uint32_t reserved6_31 : 26; /*!< Reserved. */ 99 } b; /*!< Register bits. */ 100 } sio_v151_intstatus_data_t; 101 102 /** 103 * @brief This union represents the bit fields in the sio_intclr register. 104 * Read the register into the <i>d32</i> member then 105 * set/clear the bits using the <i>b</i> elements. 106 */ 107 typedef union sio_v151_intclr_data { 108 uint32_t d32; /*!< Raw register data. */ 109 struct { 110 uint32_t rx_intr : 1; /*!< The interrupt when rx fifo above threshold. */ 111 uint32_t tx_intr : 1; /*!< The interrupt when tx fifo above threshold. */ 112 uint32_t rx_right_fifo_over : 1; /*!< The interrupt when right tx fifo overflow. */ 113 uint32_t rx_left_fifo_over : 1; /*!< The interrupt when left tx fifo overflow. */ 114 uint32_t tx_right_fifo_under : 1; /*!< The interrupt when right tx fifo underflow. */ 115 uint32_t tx_left_fifo_under : 1; /*!< The interrupt when left tx fifo underflow. */ 116 uint32_t reserved6_31 : 26; /*!< Reserved. */ 117 } b; /*!< Register bits. */ 118 } sio_v151_intclr_data_t; 119 120 /** 121 * @brief This union represents the bit fields in the sio_i2s_left_xd register. 122 * Read the register into the <i>d32</i> member then 123 * set/clear the bits using the <i>b</i> elements. 124 */ 125 typedef union sio_v151_i2s_left_xd_data { 126 uint32_t d32; /*!< Raw register data. */ 127 struct { 128 uint32_t tx_left_data : 32; /*!< Send left channel data. */ 129 } b; /*!< Register bits. */ 130 } sio_v151_i2s_left_xd_data_t; 131 132 /** 133 * @brief This union represents the bit fields in the sio_i2s_right_xd register. 134 * Read the register into the <i>d32</i> member then 135 * set/clear the bits using the <i>b</i> elements. 136 */ 137 typedef union sio_v151_i2s_right_xd_data { 138 uint32_t d32; /*!< Raw register data. */ 139 struct { 140 uint32_t tx_right_data : 32; /*!< Send right channel data. */ 141 } b; /*!< Register bits. */ 142 } sio_v151_i2s_right_xd_data_t; 143 144 /** 145 * @brief This union represents the bit fields in the sio_i2s_left_rd register. 146 * Read the register into the <i>d32</i> member then 147 * set/clear the bits using the <i>b</i> elements. 148 */ 149 typedef union sio_v151_i2s_left_rd_data { 150 uint32_t d32; /*!< Raw register data. */ 151 struct { 152 uint32_t rx_left_data : 32; /*!< Recevie left channel data. */ 153 } b; /*!< Register bits. */ 154 } sio_v151_i2s_left_rd_data_t; 155 156 /** 157 * @brief This union represents the bit fields in the sio_i2s_right_xd register. 158 * Read the register into the <i>d32</i> member then 159 * set/clear the bits using the <i>b</i> elements. 160 */ 161 typedef union sio_v151_i2s_right_rd_data { 162 uint32_t d32; /*!< Raw register data. */ 163 struct { 164 uint32_t rx_right_data : 32; /*!< Recevie right channel data. */ 165 } b; /*!< Register bits. */ 166 } sio_v151_i2s_right_rd_data_t; 167 /** 168 * @brief This union represents the bit fields in the sio_ct_set register. 169 * Read the register into the <i>d32</i> member then 170 * set/clear the bits using the <i>b</i> elements. 171 */ 172 typedef union sio_v151_ct_set_data { 173 uint32_t d32; /*!< Raw register data. */ 174 struct { 175 uint32_t reserved0_3 : 4; /*!< Reserved. */ 176 uint32_t reserved4_7 : 4; /*!< Reserved. */ 177 uint32_t tx_data_merge_en : 1; /*!< tx data merge enable. 178 0: disable. 179 1: enable. */ 180 uint32_t rx_data_merge_en : 1; /*!< rx data merge enable. 181 0: disable. 182 1: enable. */ 183 uint32_t tx_fifo_disable : 1; /*!< tx fifo disable. 184 0: disable. 185 1: enable. */ 186 uint32_t rx_fifo_disable : 1; /*!< rx fifo disable. 187 0: disable. 188 1: enable. */ 189 uint32_t tx_enable : 1; /*!< tx channel disable. 190 0: disable. 191 1: enable. */ 192 uint32_t rx_enable : 1; /*!< rx channel disable. 193 0: disable. 194 1: enable. */ 195 uint32_t intr_en : 1; /*!< Global interrupt enable. 196 0: disable. 197 1: enable. */ 198 uint32_t rst_n : 1; /*!< SIO channel reset. */ 199 uint32_t reserved16_31 : 16; /*!< Reserved. */ 200 } b; /*!< Register bits. */ 201 } sio_v151_ct_set_data_t; 202 203 /** 204 * @brief This union represents the bit fields in the sio_ct_clr register. 205 * Read the register into the <i>d32</i> member then 206 * set/clear the bits using the <i>b</i> elements. 207 */ 208 typedef union sio_v151_ct_clr_data { 209 uint32_t d32; /*!< Raw register data. */ 210 struct { 211 uint32_t reserved0_3 : 4; /*!< Reserved. */ 212 uint32_t reserved4_7 : 4; /*!< Reserved. */ 213 uint32_t tx_data_merge_en : 1; /*!< tx data merge enable. 214 0: disable. 215 1: enable. */ 216 uint32_t rx_data_merge_en : 1; /*!< rx data merge enable. 217 0: disable. 218 1: enable. */ 219 uint32_t tx_fifo_disable : 1; /*!< tx fifo disable. 220 0: disable. 221 1: enable. */ 222 uint32_t rx_fifo_disable : 1; /*!< rx fifo disable. 223 0: disable. 224 1: enable. */ 225 uint32_t tx_enable : 1; /*!< tx channel disable. 226 0: disable. 227 1: enable. */ 228 uint32_t rx_enable : 1; /*!< rx channel disable. 229 0: disable. 230 1: enable. */ 231 uint32_t intr_en : 1; /*!< Global interrupt enable. 232 0: disable. 233 1: enable. */ 234 uint32_t rst_n : 1; /*!< SIO channel reset. */ 235 uint32_t reserved16_31 : 16; /*!< Reserved. */ 236 } b; /*!< Register bits. */ 237 } sio_v151_ct_clr_data_t; 238 239 /** 240 * @brief This union represents the bit fields in the sio_fifo_threshold register. 241 * Read the register into the <i>d32</i> member then 242 * set/clear the bits using the <i>b</i> elements. 243 */ 244 typedef union sio_v151_fifo_threshold_data { 245 uint32_t d32; /*!< Raw register data. */ 246 struct { 247 uint32_t tx_fifo_threshold : 8; /*!< Receive fifo threshold. */ 248 uint32_t rx_fifo_threshold : 8; /*!< Send fifo threshold. */ 249 uint32_t reserved16_31 : 16; /*!< Reserved. */ 250 } b; /*!< Register bits. */ 251 } sio_v151_fifo_threshold_data_t; 252 253 /** 254 * @brief This union represents the bit fields in the sio_rx_sta register. 255 * Read the register into the <i>d32</i> member then 256 * set/clear the bits using the <i>b</i> elements. 257 */ 258 typedef union sio_v151_rx_sta_data { 259 uint32_t d32; /*!< Raw register data. */ 260 struct { 261 uint32_t rx_left_depth : 8; /*!< rx left depth. */ 262 uint32_t rx_right_depth : 8; /*!< rx right depth. */ 263 uint32_t reserved16_31 : 16; /*!< Reserved. */ 264 } b; /*!< Register bits. */ 265 } sio_v151_rx_sta_data_t; 266 267 /** 268 * @brief This union represents the bit fields in the sio_tx_sta register. 269 * Read the register into the <i>d32</i> member then 270 * set/clear the bits using the <i>b</i> elements. 271 */ 272 typedef union sio_v151_tx_sta_data { 273 uint32_t d32; /*!< Raw register data. */ 274 struct { 275 uint32_t tx_left_depth : 8; /*!< tx left depth. */ 276 uint32_t tx_right_depth : 8; /*!< tx right depth. */ 277 uint32_t reserved16_31 : 16; /*!< Reserved. */ 278 } b; /*!< Register bits. */ 279 } sio_v151_tx_sta_data_t; 280 281 /** 282 * @brief This union represents the bit fields in the sio_data_width_set register. 283 * Read the register into the <i>d32</i> member then 284 * set/clear the bits using the <i>b</i> elements. 285 */ 286 typedef union sio_v151_data_width_set_data { 287 uint32_t d32; /*!< Raw register data. */ 288 struct { 289 uint32_t tx_mode : 3; /*!< tx data width set data. */ 290 uint32_t rx_mode : 3; /*!< rx data width set data. */ 291 uint32_t reserved6_31 : 26; /*!< Reserved. */ 292 } b; /*!< Register bits. */ 293 } sio_v151_data_width_set_data_t; 294 295 /** 296 * @brief This union represents the bit fields in the sio_i2s_start_pos register. 297 * Read the register into the <i>d32</i> member then 298 * set/clear the bits using the <i>b</i> elements. 299 */ 300 typedef union sio_v151_i2s_start_pos_data { 301 uint32_t d32; /*!< Raw register data. */ 302 struct { 303 uint32_t start_post_read : 1; /*!< This bit indicates which channel start read. 304 0: left channel. 305 1: right channel. */ 306 uint32_t start_pos_write : 1; /*!< This bit indicates which channel start write. 307 0: left channel. 308 1: right channel. */ 309 uint32_t reserved2_31 : 30; /*!< Reserved. */ 310 } b; /*!< Register bits. */ 311 } sio_v151_i2s_start_pos_data_t; 312 313 /** 314 * @brief This union represents the bit fields in the sio_pos_flag register. 315 * Read the register into the <i>d32</i> member then 316 * set/clear the bits using the <i>b</i> elements. 317 */ 318 typedef union sio_v151_pos_flag_data { 319 uint32_t d32; /*!< Raw register data. */ 320 struct { 321 uint32_t start_post_read : 1; /*!< This bit indicates which channel start read. 322 0: left channel. 323 1: right channel. */ 324 uint32_t start_pos_write : 1; /*!< This bit indicates which channel start write. 325 0: left channel. 326 1: right channel. */ 327 uint32_t reserved2_31 : 30; /*!< Reserved. */ 328 } b; /*!< Register bits. */ 329 } sio_v151_pos_flag_data_t; 330 331 /** 332 * @brief This union represents the bit fields in the sio_signed_ext register. 333 * Read the register into the <i>d32</i> member then 334 * set/clear the bits using the <i>b</i> elements. 335 */ 336 typedef union sio_v151_signed_ext_data { 337 uint32_t d32; /*!< Raw register data. */ 338 struct { 339 uint32_t signed_ext_en : 1; /*!< Upper bit data symbol extension enable. 340 0: disable. 341 1: enable. */ 342 uint32_t reserved1_31 : 31; /*!< Reserved. */ 343 } b; /*!< Register bits. */ 344 } sio_v151_signed_ext_data_t; 345 346 /** 347 * @brief This union represents the bit fields in the sio_i2s_pos_merge_en register. 348 * Read the register into the <i>d32</i> member then 349 * set/clear the bits using the <i>b</i> elements. 350 */ 351 typedef union sio_v151_i2s_pos_merge_en_data { 352 uint32_t d32; /*!< Raw register data. */ 353 struct { 354 uint32_t merge_en : 1; /*!< I2S pos merge enable. 355 0: disable. 356 1: enable. */ 357 uint32_t reserved1_31 : 31; /*!< Reserved. */ 358 } b; /*!< Register bits. */ 359 } sio_v151_i2s_pos_merge_en_data_t; 360 361 /** 362 * @brief This union represents the bit fields in the sio_intmask register. 363 * Read the register into the <i>d32</i> member then 364 * set/clear the bits using the <i>b</i> elements. 365 */ 366 typedef union sio_v151_intmask_data { 367 uint32_t d32; /*!< Raw register data. */ 368 struct { 369 uint32_t rx_int : 1; /*!< Mask the interrupt when rx fifo above threshold. 370 0: disable. 371 1: enable. */ 372 uint32_t tx_intr : 1; /*!< Mask the interrupt when tx fifo above threshold. 373 0: disable. 374 1: enable. */ 375 uint32_t rx_right_fifo_over : 1; /*!< Mask the interrupt when right rx fifo overflow. 376 0: disable. 377 1: enable. */ 378 uint32_t rx_left_fifo_over : 1; /*!< Mask the interrupt when left rx fifo overflow. 379 0: disable. 380 1: enable. */ 381 uint32_t tx_right_fifo_under : 1; /*!< Mask the interrupt when right tx fifo underflow. 382 0: disable 383 1: enable. */ 384 uint32_t tx_left_fifo_under : 1; /*!< Mask the interrupt when left tx fifo underflow. 385 0: disable. 386 1: enable. */ 387 uint32_t reserved6_31 : 26; /*!< Reserved. */ 388 } b; /*!< Register bits. */ 389 } sio_v151_intmask_data_t; 390 391 /** 392 * @brief This union represents the bit fields in the cfg_i2s_crg register. 393 * Read the register into the <i>d32</i> member then 394 * set/clear the bits using the <i>b</i> elements. 395 */ 396 typedef union sio_v151_i2s_crg_data { 397 uint32_t d32; /*!< Raw register data. */ 398 struct { 399 uint32_t i2s_bclk_div_en : 1; /*!< bclk enable signal. */ 400 uint32_t i2s_crg_clken : 1; /*!< bclk enable signal is invalid. */ 401 uint32_t i2s_bclk_sel : 1; /*!< bclk phase. */ 402 uint32_t reserved4 : 1; /*!< Reserved. */ 403 uint32_t i2s_fs_sel : 1; /*!< bclk phase. */ 404 uint32_t reserved5_15 : 11; /*!< Reserved. */ 405 } b; /*!< Register bits. */ 406 } sio_v151_i2s_crg_data_t; 407 408 /** 409 * @brief This union represents the bit fields in the cfg_i2s_bclk_div_num register. 410 * Read the register into the <i>d32</i> member then 411 * set/clear the bits using the <i>b</i> elements. 412 */ 413 typedef union sio_v151_i2s_bclk_div_num_data { 414 uint32_t d32; /*!< Raw register data. */ 415 struct { 416 uint32_t bclk_div_num : 7; /*!< Frequency division of the bclk frequency divider. */ 417 uint32_t reserved7_15 : 8; /*!< Reserved. */ 418 } b; /*!< Register bits. */ 419 } sio_v151_i2s_bclk_div_num_data_t; 420 421 /** 422 * @brief This union represents the bit fields in the cfg_i2s_fs_div_num register. 423 * Read the register into the <i>d32</i> member then 424 * set/clear the bits using the <i>b</i> elements. 425 */ 426 typedef union sio_v151_i2s_fs_div_num_data { 427 uint32_t d32; /*!< Raw register data. */ 428 struct { 429 uint32_t fs_div_num : 10; /*!< Frequency divisionof the fsclk frequency divider. */ 430 uint32_t reserved10_15 : 5; /*!< Reserved. */ 431 } b; /*!< Register bits. */ 432 } sio_v151_i2s_fs_div_num_data_t; 433 434 /** 435 * @brief This union represents the bit fields in the cfg_i2s_fs_div_num register. 436 * Read the register into the <i>d32</i> member then 437 * set/clear the bits using the <i>b</i> elements. 438 */ 439 typedef union sio_v151_i2s_fs_div_ratio_num_data { 440 uint32_t d32; /*!< Raw register data. */ 441 struct { 442 uint32_t fs_div_ratio_num : 11; /*!< Frequency division ratio of the fsclk frequency divider. */ 443 uint32_t reserved11_15 : 4; /*!< Reserved. */ 444 } b; /*!< Register bits. */ 445 } sio_v151_i2s_fs_div_ratio_num_data_t; 446 447 /** 448 * @brief This union represents the bit fields in the sio_i2s_dual_rx_chn register. 449 * Read the register into the <i>d32</i> member then 450 * set/clear the bits using the <i>b</i> elements. 451 */ 452 typedef union sio_v151_i2s_dual_rx_chn_data { 453 uint32_t d32; /*!< Raw register data. */ 454 struct { 455 uint32_t rx_data : 32; /*!< Receive data. */ 456 } b; /*!< Register bits. */ 457 } sio_v151_i2s_dual_rx_chn_data_t; 458 459 /** 460 * @brief This union represents the bit fields in the sio_i2s_dual_tx_chn register. 461 * Read the register into the <i>d32</i> member then 462 * set/clear the bits using the <i>b</i> elements. 463 */ 464 typedef union sio_v151_i2s_dual_tx_chn_data { 465 uint32_t d32; /*!< Raw register data. */ 466 struct { 467 uint32_t tx_data : 32; /*!< Send data. */ 468 } b; /*!< Register bits. */ 469 } sio_v151_i2s_dual_tx_chn_data_t; 470 471 /** 472 * @brief Registers associated with Sio. 473 */ 474 typedef struct sio_v151_regs { 475 volatile uint32_t version; /*!< sio_version. <i>Offset: 3Ch</i>. */ 476 volatile uint32_t mode; /*!< sio_mode. <i>Offset: 40h</i>. */ 477 volatile uint32_t intstatus; /*!< sio_intstatus. <i>Offset: 44h</i>. */ 478 volatile uint32_t intclr; /*!< sio_intclr. <i>Offset: 48h</i>. */ 479 volatile uint32_t left_tx; /*!< sio_left_tx. <i>Offset: 4Ch</i>. */ 480 volatile uint32_t right_tx; /*!< sio_right_tx. <i>Offset: 50h</i>. */ 481 volatile uint32_t left_rx; /*!< sio_left_rx. <i>Offset: 54h</i>. */ 482 volatile uint32_t right_rx; /*!< sio_right_rx. <i>Offset: 58h</i>. */ 483 volatile uint32_t ct_set; /*!< sio_ct_set. <i>Offset: 5Ch</i>. */ 484 volatile uint32_t ct_clr; /*!< sio_ct_clr. <i>Offset: 60h</i>. */ 485 volatile uint32_t fifo_threshold; /*!< sio_fifo_threshold. <i>Offset: 64h</i>. */ 486 volatile uint32_t rx_sta; /*!< sio_rx_sta. <i>Offset: 68h</i>. */ 487 volatile uint32_t tx_sta; /*!< sio_tx_sta. <i>Offset: 6Ch</i>. */ 488 volatile uint32_t reserved_reg[2]; /*!< reserved_reg. <i>Offset: 70h</i>. */ 489 volatile uint32_t data_width_set; /*!< sio_data_width_set. <i>Offset: 78h</i>. */ 490 volatile uint32_t i2s_start_pos; /*!< sio_i2s_start_pos. <i>Offset: 7Ch</i>. */ 491 volatile uint32_t i2s_pos_flag; /*!< sio_i2s_pos_flag. <i>Offset:80h</i>. */ 492 volatile uint32_t signed_ext; /*!< sio_signed_ext. <i>Offset: 84h</i>. */ 493 volatile uint32_t i2s_pos_merge_en; /*!< sio_i2s_pos_merge_en. <i>Offset: 88h</i>. */ 494 volatile uint32_t intmask; /*!< sio_intmask. <i>Offset: 8Ch</i>. */ 495 volatile uint32_t i2s_crg; /*!< cfg_i2s_crg. <i>Offset: 90h</i>. */ 496 volatile uint32_t i2s_bclk_div_num; /*!< cfg_i2s_bclk_div_num. <i>Offset: 94h</i>. */ 497 volatile uint32_t i2s_fs_div_num; /*!< cfg_i2s_fs_div_num. <i>Offset: 98h</i>. */ 498 volatile uint32_t i2s_fs_div_ratio_num; /*!< cfg_volatile . <i>Offset: 9Ch</i>. */ 499 volatile uint32_t i2s_dual_rx_chn; /*!< sio_i2s_dual_rx_chn. <i>Offset: A0h</i>. */ 500 volatile uint32_t reserved_reg1[7]; /*!< sio_version. <i>Offset: A4h</i>. */ 501 volatile uint32_t i2s_dual_tx_chn; /*!< sio_i2s_dual_tx_chn. <i>Offset: C0h</i>. */ 502 } sio_v151_regs_t; 503 504 /** 505 * @} 506 */ 507 508 #ifdef __cplusplus 509 #if __cplusplus 510 } 511 #endif /* __cplusplus */ 512 #endif /* __cplusplus */ 513 514 #endif