1 /*
2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19 #ifndef __VOU_VOU_H__
20 #define __VOU_VOU_H__
21
22 #include "hi_osal.h"
23 #include "hi_defines.h"
24 #include "hi_debug_adapt.h"
25 #include "vou_drv.h"
26 #include "hi_common_adapt.h"
27 #include "hi_math_adapt.h"
28 #include "vou_dev_exp.h"
29 #include "securec.h"
30
31 #ifdef __cplusplus
32 #if __cplusplus
33 extern "C" {
34 #endif
35 #endif /* end of #ifdef __cplusplus */
36
37 #define VOU_STATE_STARTED 0
38 #define VOU_STATE_STOPPING 1
39 #define VOU_STATE_STOPPED 2
40
41 #define MDDRC_ZONE_MAX_NUM 32
42 #define VHD_MAX_CHN_NUM 1 /* max VHD chn num */
43 #define VO_MAX_GFX_LAYER_PER_DEV 1
44 #define VO_MIN_CHN_LINE 3
45 #define VO_DEF_CHN_BUF_LEN 8
46 #define VO_DEF_DISP_BUF_LEN 5
47 #define VO_DEF_VIRT_BUF_LEN 3
48 #define VO_DEF_WBC_DEPTH_LEN 8
49
50 /* WBC channel id */
51 #define VO_WBC_CHN_ID (VO_MAX_CHN_NUM + 1)
52 #define VO_DEFAULT_CHN (-1) /* use vo buffer as pip buffer */
53
54 #define VO_INVALID_DEV (-1) /* invalid device tag */
55
56 #define VO_CHN_MAX_BLK 4 /* channel buffer node limit */
57 #define VO_CHN_MAX_NODE 10 /* channel free list node limit */
58 #define VO_HD_DISP_MIN_BLK 4 /* display buffer node limit */
59 #define VO_SD_DISP_MIN_BLK 3 /* display buffer node limit */
60 #define VO_SD_DISP_MIN_BLK_SBM 2 /* display buffer node limit save buff mode */
61
62 #define VO_DISP_MAX_BLK 15 /* display buffer node limit */
63
64 #define VO_PRIORITY_MAX VO_MAX_CHN_NUM /* priority max value on device */
65 #define VO_CHN_PRIORITY_MAX VO_MAX_CHN_NUM
66
67 #define VO_HD_PIP_MAX_SIZE 2073600 /* 1920 * 1080 */
68
69 #define VO_HD_DISP_THD 3
70
71 #define PTS_SPAN_TOLERATION 10000000 /* tolerance of error frame PTS, set 10s */
72
73 #define VO_PIP_MIN_WIDTH 32 /* minimize pip width */
74 #define VO_PIP_MIN_HEIGHT 32 /* minimize pip height */
75
76 #define VO_BKGRD_COLOR_RED 0xFF0000 /* red background color */
77 #define VO_BKGRD_COLOR_GREEN 0x00FF00 /* green background color */
78 #define VO_BKGRD_COLOR_BLUE 0x0000FF /* blue background color */
79 #define VO_BKGRD_COLOR_YELLOW ((VO_BKGRD_COLOR_RED) + (VO_BKGRD_COLOR_GREEN))
80 #define VO_BKGRD_COLOR_CYAN ((VO_BKGRD_COLOR_GREEN) + (VO_BKGRD_COLOR_BLUE))
81 #define VO_BKGRD_COLOR_MAGENTA ((VO_BKGRD_COLOR_BLUE) + (VO_BKGRD_COLOR_RED))
82
83 #define VO_BKGRD_COLOR_WHITE 0xFFFFFF /* white background color */
84 #define VO_BKGRD_COLOR_BLACK 0x000000 /* black back groud color */
85
86 #define VO_ALPHA_TRANSPARENT 0x0 /* transparent alpha */
87 #define VO_ALPHA_OPACITY 0xFF /* opacity alpha */
88
89 #define VO_CHN_VI_BUF_LINE VO_MIN_CHN_LINE /* channel buffer waterline of preview */
90
91 #define VO_TIMER_EXPIRES 10 /* virtual device timer expires (ms) */
92
93 #define VO_MAX_SYNC_WIDTH 5000
94 #define VO_MAX_SYNC_HEIGHT 5000
95
96 #define VOU_MAX_OSD_NUM OVERLAYEX_MAX_NUM_VO
97 #define VOU_MAX_COVER_NUM COVEREX_MAX_NUM_VO
98 #define VOU_LUMA_STAT_NUM 64
99
100 #define VOU_REGION_LUMA_BUFFER_SIZE (VOU_LUMA_STAT_NUM * LUMA_PHY_ALIGN)
101
102 /* the align format of memory assign */
103 #define VO_W_ALIGN_16BYTE 16
104 #define vo_align(x, a) (((x) + (a)-1) & (~((a) - 1)))
105 #define VO_MAX_LINE_FOR_ALIGN (64 * VO_W_ALIGN_16BYTE)
106
107 #define VO_HD_MIN_VTTH_WATERLINE 240
108 #define VO_HD_MAX_VTTH_WATERLINE 8191
109 #define VO_SD_MIN_VTTH_WATERLINE 100
110 #define VO_SD_MAX_VTTH_WATERLINE 8191
111 #define VO_HD_MIN_VTTH_WATERLINE2 2
112 #define VO_SD_MIN_VTTH_WATERLINE2 2
113
114 #define VO_MAX_MUX_NUM 3
115 #define VO_MAX_INTFNAME_LEN 10
116 #define VO_MAX_INTF_TYPE_NUM 16
117
118 #define VO_WBC_OUT_MAX_WIDTH 4096
119 #define VO_WBC_OUT_MAX_HEIGHT 4096
120
121 #define VO_RECT_ALIGN 2
122 #define VO_RGN_LUMA_ALIGN 2
123 #define VO_CHN_DISP_POS_ALIGN 2
124
125 #define VO_MAX_ALPHA_VAL 255
126
127 #define VO_CHN_QRY_WAIT_TIMEOUT 4000
128 #define VO_WBC_BG_BLACK_WAIT_TIMEOUT 4000
129 #define VO_DISABLE_LAYER_WAIT_TIMEOUT 1000
130 #define VO_CLEAR_BUF_WAIT_TIMEOUT 1000
131 #define VO_DISABLE_WBC_TIMEOUT 500000
132 #define VO_TIME_ONE_SECOND_UNIT_MICROSECOND 1000000
133 #define VO_TIME_TEN_SECONDS_UNIT_MICROSECOND 10000000ul
134
135 typedef struct {
136 hi_s32 layer_id;
137 } vo_wait_layer;
138
139 typedef struct {
140 hi_s32 layer_id;
141 hi_s32 chn_id;
142 hi_s32 last_node_num;
143 hi_s32 unique_id;
144 } vo_wait_chn;
145
146 typedef struct {
147 hi_s32 wbc_id;
148 } vo_wait_wbc;
149
150 /* typical value of display frequency */
151 typedef enum {
152 VO_DISP_FREQ_VGA75 = 75,
153 VO_DISP_FREQ_VGA = 60,
154 VO_DISP_FREQ_VGA30 = 30,
155 VO_DISP_FREQ_VGA25 = 25,
156 VO_DISP_FREQ_24P = 24,
157 VO_DISP_FREQ_50P = 50,
158 VO_DISP_FREQ_PAL = 25,
159 VO_DISP_FREQ_NTSC = 30,
160 VO_DISP_FREQ_BUTT
161 } vo_disp_freq;
162
163 /* typical value of video size */
164 typedef enum {
165 VO_DISP_1080_WIDTH = 1920,
166 VO_DISP_1080_HEIGHT = 1080,
167 VO_DISP_720P_WIDTH = 1280,
168 VO_DISP_720P_HEIGHT = 720,
169 VO_DISP_D1_WIDTH = 720,
170 VO_DISP_D1P_HEIGH = 576,
171 VO_DISP_D1N_HEIGH = 480,
172 VO_DISP_VGA_1024 = 1024,
173 VO_DISP_VGA_768 = 768,
174 VO_DISP_VGA_800 = 800,
175 VO_DISP_VGA_600 = 600,
176 VO_DISP_VIRT_WIDTH = 5000,
177 VO_DISP_VIRT_HEIGHT = 5000,
178 VO_DISP_8K_WIDTH = 8192,
179 VO_DISP_8K_HEIGHT = 4320,
180 VO_DISP_BUTT
181 } vo_disp_size;
182
183 /* define vo receive frame info */
184 typedef struct {
185 hi_bool suc;
186 hi_mod_id mod_id;
187 hi_bool block;
188 hi_video_frame_info *video_frame[2];
189 hi_u64 node_index;
190 } vo_recv_frame_info;
191
192 typedef struct {
193 hi_u32 luma; /* luminance: 0 ~ 100 default: 50 */
194 hi_u32 contrast; /* contrast: 0 ~ 100 default: 50 */
195 hi_u32 hue; /* hue: 0 ~ 100 default: 50 */
196 hi_u32 satuature; /* satuature: 0 ~ 100 default: 50 */
197 } vo_csc_val;
198
199 typedef struct {
200 hi_u64 scale_pts; /* scale pts which will be display next time */
201 osal_timer_t timer; /* virtual device timer */
202 } vou_virt_dev;
203
204 typedef struct {
205 hi_bool load_detect_enable;
206 hi_u32 int_cur_count;
207 hi_u32 int_max_count;
208 } vou_load_detect_info;
209
210 typedef struct {
211 hi_u32 int_rate;
212 hi_u32 int_count;
213 hi_u64 last_rate_time;
214
215 hi_u32 int_tmp;
216 hi_u32 int_time_per_min_tmp;
217 hi_u32 int_time_per_min;
218
219 hi_u32 int_time;
220 hi_u32 max_int_time;
221
222 hi_u64 last_int_time;
223 hi_u32 int_gap_time;
224 hi_u32 max_int_gap_time;
225
226 hi_u64 last_time;
227 } vo_debug_info;
228
229 typedef struct {
230 hi_bool vo_enable;
231 hi_bool config;
232
233 hi_bool wbc_bind;
234 hi_vo_wbc wbc;
235
236 hi_vo_pub_attr vou_attr;
237
238 hi_u32 max_width;
239 hi_u32 max_height;
240
241 hi_u32 full_frame_rate;
242
243 vo_int_mode vo_int_type;
244
245 hi_u32 time_ref;
246
247 hi_u64 coef_addr_phys;
248 hi_void *coef_addr_virt;
249
250 vou_load_detect_info load_detect_info;
251 vo_debug_info debug_info;
252
253 vo_dither_info dither_info;
254
255 hi_vo_user_intfsync_info vo_user_sync_info;
256 } vo_dev_info;
257
258 typedef struct {
259 hi_vo_intf_sync index;
260 hi_char *name;
261 hi_u32 width;
262 hi_u32 height;
263 hi_u32 frame_rate;
264 } vo_sync_basic_info;
265
vo_init_lock(osal_spinlock_t * lock)266 __inline static hi_s32 vo_init_lock(osal_spinlock_t *lock)
267 {
268 osal_spin_lock_init(lock);
269 return HI_SUCCESS;
270 }
271
vo_deinit_lock(osal_spinlock_t * lock)272 __inline static hi_s32 vo_deinit_lock(osal_spinlock_t *lock)
273 {
274 osal_spin_lock_destroy(lock);
275 return HI_SUCCESS;
276 }
277
vo_spin_lock(osal_spinlock_t * lock,hi_u32 * flag)278 __inline static hi_s32 vo_spin_lock(osal_spinlock_t *lock, hi_u32 *flag)
279 {
280 unsigned long tmp_flag = (unsigned long)(*flag);
281 osal_spin_lock_irqsave(lock, &tmp_flag);
282 *flag = (hi_u32)tmp_flag;
283 return HI_SUCCESS;
284 }
285
vo_spin_unlock(osal_spinlock_t * lock,hi_u32 * flag)286 __inline static hi_s32 vo_spin_unlock(osal_spinlock_t *lock, hi_u32 *flag)
287 {
288 unsigned long tmp_flag = (unsigned long)(*flag);
289 osal_spin_unlock_irqrestore(lock, &tmp_flag);
290 *flag = (hi_u32)tmp_flag;
291 return HI_SUCCESS;
292 }
293
294 hi_u32 vo_get_vo_state(hi_void);
295 osal_spinlock_t *vo_get_dev_lock(hi_void);
296 osal_spinlock_t *vo_get_list_lock(hi_void);
297 osal_spinlock_t *vo_get_wbc_lock(hi_void);
298 struct osal_semaphore *vo_get_chn_sem(hi_void);
299 struct osal_semaphore *vo_get_dev_sem(hi_void);
300 hi_vo_mod_param *vo_get_vo_mod_param(hi_void);
301 vo_dev_info *vo_get_dev_ctx(hi_vo_dev vo_dev);
302 vou_virt_dev *vo_get_virt_dev_ctx(hi_vo_dev vo_dev);
303 hi_u32 vo_get_transparent_transmit(hi_void);
304 vou_export_callback_s *vo_get_exp_callback(hi_void);
305 vo_sync_basic_info *vo_get_sync_basic_info(hi_void);
306
307 #define vo_down_sem_return() \
308 do { \
309 struct osal_semaphore *dev_sem_; \
310 dev_sem_ = vo_get_dev_sem(); \
311 if (osal_down_interruptible(dev_sem_)) \
312 return -ERESTARTSYS; \
313 } while (0)
314
315 #define vo_up_sem() \
316 do { \
317 struct osal_semaphore *dev_sem_; \
318 dev_sem_ = vo_get_dev_sem(); \
319 osal_up(dev_sem_); \
320 } while (0)
321
322 #define vo_down_chn_sem_return() \
323 do { \
324 struct osal_semaphore *chn_sem_; \
325 chn_sem_ = vo_get_chn_sem(); \
326 if (osal_down_interruptible(chn_sem_)) \
327 return -ERESTARTSYS; \
328 } while (0)
329
330 #define vo_up_chn_sem() \
331 do { \
332 struct osal_semaphore *chn_sem_; \
333 chn_sem_ = vo_get_chn_sem(); \
334 osal_up(chn_sem_); \
335 } while (0)
336
337 #define vo_dev_spin_lock(flags) \
338 do { \
339 osal_spinlock_t * lock_ = vo_get_dev_lock(); \
340 vo_spin_lock(lock_, flags); \
341 } while (0)
342
343 #define vo_dev_spin_unlock(flags) \
344 do { \
345 osal_spinlock_t * lock_ = vo_get_dev_lock(); \
346 vo_spin_unlock(lock_, flags); \
347 } while (0)
348
349 #define vo_list_spin_lock(flags) \
350 do { \
351 osal_spinlock_t * lock_ = vo_get_list_lock(); \
352 vo_spin_lock(lock_, flags); \
353 } while (0)
354
355 #define vo_list_spin_unlock(flags) \
356 do { \
357 osal_spinlock_t * lock_ = vo_get_list_lock(); \
358 vo_spin_unlock(lock_, flags); \
359 } while (0)
360
361 #ifdef CONFIG_HI_VO_WBC
362 #define vo_wbc_spin_lock(flags) \
363 do { \
364 osal_spinlock_t * lock_ = vo_get_wbc_lock(); \
365 vo_spin_lock(lock_, flags); \
366 } while (0)
367
368 #define vo_wbc_spin_unlock(flags) \
369 do { \
370 osal_spinlock_t * lock_ = vo_get_wbc_lock(); \
371 vo_spin_unlock(lock_, flags); \
372 } while (0)
373 #endif
374
375 #ifdef CONFIG_HI_VO_BATCH
376 hi_s32 vou_trave_batch_cmd(hi_vo_dev dev, hi_bool exc, hi_u32 *list_flag);
377 #endif
378
379 #ifdef __cplusplus
380 #if __cplusplus
381 }
382 #endif
383 #endif /* end of #ifdef __cplusplus */
384
385 #endif /* end of #ifdef __VOU_VOU_H__ */
386