Home
last modified time | relevance | path

Searched +full:0 +full:x0900 (Results 1 – 25 of 311) sorted by relevance

12345678910>>...13

/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
Dclk-exynos7.c13 /* Register Offset definitions for CMU_TOPC (0x10570000) */
14 #define CC_PLL_LOCK 0x0000
15 #define BUS0_PLL_LOCK 0x0004
16 #define BUS1_DPLL_LOCK 0x0008
17 #define MFC_PLL_LOCK 0x000C
18 #define AUD_PLL_LOCK 0x0010
19 #define CC_PLL_CON0 0x0100
20 #define BUS0_PLL_CON0 0x0110
21 #define BUS1_DPLL_CON0 0x0120
22 #define MFC_PLL_CON0 0x0130
[all …]
/kernel/linux/linux-6.6/drivers/clk/samsung/
Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
Dclk-exynos7.c13 /* Register Offset definitions for CMU_TOPC (0x10570000) */
14 #define CC_PLL_LOCK 0x0000
15 #define BUS0_PLL_LOCK 0x0004
16 #define BUS1_DPLL_LOCK 0x0008
17 #define MFC_PLL_LOCK 0x000C
18 #define AUD_PLL_LOCK 0x0010
19 #define CC_PLL_CON0 0x0100
20 #define BUS0_PLL_CON0 0x0110
21 #define BUS1_DPLL_CON0 0x0120
22 #define MFC_PLL_CON0 0x0130
[all …]
/kernel/linux/linux-5.10/include/pcmcia/
Dciscode.h17 #define MANFID_3COM 0x0101
18 #define PRODID_3COM_3CXEM556 0x0035
19 #define PRODID_3COM_3CCFEM556 0x0556
20 #define PRODID_3COM_3C562 0x0562
22 #define MANFID_ACCTON 0x01bf
23 #define PRODID_ACCTON_EN2226 0x010a
25 #define MANFID_ADAPTEC 0x012f
26 #define PRODID_ADAPTEC_SCSI 0x0001
28 #define MANFID_ATT 0xffff
29 #define PRODID_ATT_KIT 0x0100
[all …]
/kernel/linux/linux-6.6/include/pcmcia/
Dciscode.h17 #define MANFID_3COM 0x0101
18 #define PRODID_3COM_3CXEM556 0x0035
19 #define PRODID_3COM_3CCFEM556 0x0556
20 #define PRODID_3COM_3C562 0x0562
22 #define MANFID_ACCTON 0x01bf
23 #define PRODID_ACCTON_EN2226 0x010a
25 #define MANFID_ADAPTEC 0x012f
26 #define PRODID_ADAPTEC_SCSI 0x0001
28 #define MANFID_ATT 0xffff
29 #define PRODID_ATT_KIT 0x0100
[all …]
/kernel/linux/linux-5.10/drivers/media/i2c/
Dimx355.c14 #define IMX355_REG_MODE_SELECT 0x0100
15 #define IMX355_MODE_STANDBY 0x00
16 #define IMX355_MODE_STREAMING 0x01
19 #define IMX355_REG_CHIP_ID 0x0016
20 #define IMX355_CHIP_ID 0x0355
23 #define IMX355_REG_FLL 0x0340
24 #define IMX355_FLL_MAX 0xffff
27 #define IMX355_REG_EXPOSURE 0x0202
30 #define IMX355_EXPOSURE_DEFAULT 0x0282
33 #define IMX355_REG_ANALOG_GAIN 0x0204
[all …]
/kernel/linux/linux-6.6/drivers/media/i2c/
Dimx355.c14 #define IMX355_REG_MODE_SELECT 0x0100
15 #define IMX355_MODE_STANDBY 0x00
16 #define IMX355_MODE_STREAMING 0x01
19 #define IMX355_REG_CHIP_ID 0x0016
20 #define IMX355_CHIP_ID 0x0355
23 #define IMX355_REG_FLL 0x0340
24 #define IMX355_FLL_MAX 0xffff
27 #define IMX355_REG_EXPOSURE 0x0202
30 #define IMX355_EXPOSURE_DEFAULT 0x0282
33 #define IMX355_REG_ANALOG_GAIN 0x0204
[all …]
/kernel/linux/linux-5.10/arch/x86/boot/
Dvideo.h25 * of compatibility when extending the table. These are between 0x00 and 0xff.
27 #define VIDEO_FIRST_MENU 0x0000
29 /* Standard BIOS video modes (BIOS number + 0x0100) */
30 #define VIDEO_FIRST_BIOS 0x0100
32 /* VESA BIOS video modes (VESA number + 0x0200) */
33 #define VIDEO_FIRST_VESA 0x0200
35 /* Video7 special modes (BIOS number + 0x0900) */
36 #define VIDEO_FIRST_V7 0x0900
39 #define VIDEO_FIRST_SPECIAL 0x0f00
40 #define VIDEO_80x25 0x0f00
[all …]
/kernel/linux/linux-6.6/arch/x86/boot/
Dvideo.h25 * of compatibility when extending the table. These are between 0x00 and 0xff.
27 #define VIDEO_FIRST_MENU 0x0000
29 /* Standard BIOS video modes (BIOS number + 0x0100) */
30 #define VIDEO_FIRST_BIOS 0x0100
32 /* VESA BIOS video modes (VESA number + 0x0200) */
33 #define VIDEO_FIRST_VESA 0x0200
35 /* Video7 special modes (BIOS number + 0x0900) */
36 #define VIDEO_FIRST_V7 0x0900
39 #define VIDEO_FIRST_SPECIAL 0x0f00
40 #define VIDEO_80x25 0x0f00
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Dcm81xx.h13 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
14 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
15 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
16 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
19 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
20 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
21 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
24 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
25 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
26 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
Dcm2_54xx.h22 #define OMAP54XX_CM_CORE_BASE 0x4a008000
28 #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000
29 #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100
30 #define OMAP54XX_CM_CORE_COREAON_INST 0x0600
31 #define OMAP54XX_CM_CORE_CORE_INST 0x0700
32 #define OMAP54XX_CM_CORE_IVA_INST 0x1200
33 #define OMAP54XX_CM_CORE_CAM_INST 0x1300
34 #define OMAP54XX_CM_CORE_DSS_INST 0x1400
35 #define OMAP54XX_CM_CORE_GPU_INST 0x1500
36 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600
[all …]
Dcm33xx.h17 #define AM33XX_CM_BASE 0x44e00000
23 #define AM33XX_CM_PER_MOD 0x0000
24 #define AM33XX_CM_WKUP_MOD 0x0400
25 #define AM33XX_CM_DPLL_MOD 0x0500
26 #define AM33XX_CM_MPU_MOD 0x0600
27 #define AM33XX_CM_DEVICE_MOD 0x0700
28 #define AM33XX_CM_RTC_MOD 0x0800
29 #define AM33XX_CM_GFX_MOD 0x0900
30 #define AM33XX_CM_CEFUSE_MOD 0x0A00
33 #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dcm81xx.h21 #define TI81XX_CM_ACTIVE_MOD 0x0400 /* 256B */
22 #define TI81XX_CM_DEFAULT_MOD 0x0500 /* 256B */
23 #define TI81XX_CM_ALWON_MOD 0x1400 /* 1KB */
24 #define TI81XX_CM_SGX_MOD 0x0900 /* 256B */
27 #define TI816X_CM_IVAHD0_MOD 0x0600 /* 256B */
28 #define TI816X_CM_IVAHD1_MOD 0x0700 /* 256B */
29 #define TI816X_CM_IVAHD2_MOD 0x0800 /* 256B */
32 #define TI81XX_CM_ALWON_L3_SLOW_CLKDM 0x0000
33 #define TI81XX_CM_ALWON_L3_MED_CLKDM 0x0004
34 #define TI81XX_CM_ETHERNET_CLKDM 0x0004
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/kernel/linux/linux-6.6/drivers/net/fddi/skfp/h/
Dfplustm.h113 #define VOID_FRAME_OFF 0x00
114 #define CLAIM_FRAME_OFF 0x08
115 #define BEACON_FRAME_OFF 0x10
116 #define DBEACON_FRAME_OFF 0x18
117 #define RX_FIFO_OFF 0x21 /* to get a prime number for */
120 #define RBC_MEM_SIZE 0x8000
121 #define SEND_ASYNC_AS_SYNC 0x1
122 #define SYNC_TRAFFIC_ON 0x2
125 #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
126 #define TX_FIFO_SPACE 0x4000
[all …]
/kernel/linux/linux-5.10/drivers/net/fddi/skfp/h/
Dfplustm.h113 #define VOID_FRAME_OFF 0x00
114 #define CLAIM_FRAME_OFF 0x08
115 #define BEACON_FRAME_OFF 0x10
116 #define DBEACON_FRAME_OFF 0x18
117 #define RX_FIFO_OFF 0x21 /* to get a prime number for */
120 #define RBC_MEM_SIZE 0x8000
121 #define SEND_ASYNC_AS_SYNC 0x1
122 #define SYNC_TRAFFIC_ON 0x2
125 #define RX_FIFO_SPACE 0x4000 - RX_FIFO_OFF
126 #define TX_FIFO_SPACE 0x4000
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Ddra72x.dtsi27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ddra72x.dtsi27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
36 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
40 ranges = <0x0 0x5b000 0x1000>;
42 cal: cal@0 {
44 reg = <0x0000 0x400>,
45 <0x0800 0x40>,
46 <0x0900 0x40>;
51 ti,camerrx-control = <&scm_conf 0xE94>;
[all …]
/kernel/linux/patches/linux-4.19/prebuilts/usr/include/linux/
Din6.h55 #define IPV6_FL_A_GET 0
62 #define IPV6_FL_S_NONE 0
67 #define IPV6_FLOWINFO_FLOWLABEL 0x000fffff
68 #define IPV6_FLOWINFO_PRIORITY 0x0ff00000
69 #define IPV6_PRIORITY_UNCHARACTERIZED 0x0000
70 #define IPV6_PRIORITY_FILLER 0x0100
71 #define IPV6_PRIORITY_UNATTENDED 0x0200
72 #define IPV6_PRIORITY_RESERVED1 0x0300
73 #define IPV6_PRIORITY_BULK 0x0400
74 #define IPV6_PRIORITY_RESERVED2 0x0500
[all …]
/kernel/linux/linux-6.6/arch/m68k/include/asm/
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/kernel/linux/linux-5.10/arch/m68k/include/asm/
Dmcfpit.h18 #define MCFPIT_PCSR 0x0 /* PIT control register */
19 #define MCFPIT_PMR 0x2 /* PIT modulus register */
20 #define MCFPIT_PCNTR 0x4 /* PIT count register */
25 #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */
26 #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */
27 #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */
28 #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */
29 #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */
30 #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */
31 #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */
[all …]
/kernel/linux/linux-5.10/drivers/usb/serial/
Dnavman.c21 { USB_DEVICE(0x0a99, 0x0001) }, /* Talon Technology device */
22 { USB_DEVICE(0x0df7, 0x0900) }, /* Mobile Action i-gotU */
35 case 0: in navman_read_int_callback()
68 int result = 0; in navman_open()
/kernel/linux/linux-6.6/drivers/usb/serial/
Dnavman.c21 { USB_DEVICE(0x0a99, 0x0001) }, /* Talon Technology device */
22 { USB_DEVICE(0x0df7, 0x0900) }, /* Mobile Action i-gotU */
35 case 0: in navman_read_int_callback()
68 int result = 0; in navman_open()

12345678910>>...13