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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt9 Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
10 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
11 be be <0x6000c000 0x150>.
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/kernel/linux/linux-6.6/drivers/media/pci/cx18/
Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/cx18/
Dcx18-av-audio.c60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq()
61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq()
63 cx18_av_write4(cx, 0x108, 0x200d040f); in set_audclk_freq()
65 /* VID_PLL Fraction = 0x2be2fe */ in set_audclk_freq()
66 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz pre-postdiv*/ in set_audclk_freq()
67 cx18_av_write4(cx, 0x10c, 0x002be2fe); in set_audclk_freq()
69 /* AUX_PLL Fraction = 0x176740c */ in set_audclk_freq()
70 /* xtal * 0xd.bb3a060/0x20 = 32000 * 384: 393 MHz p-pd*/ in set_audclk_freq()
71 cx18_av_write4(cx, 0x110, 0x0176740c); in set_audclk_freq()
74 /* 0x1.f77f = (4 * xtal/8*2/455) / 32000 */ in set_audclk_freq()
[all …]
/kernel/linux/linux-5.10/drivers/media/i2c/cx25840/
Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
/kernel/linux/linux-6.6/drivers/media/i2c/cx25840/
Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/bt8xx/
Dbt878.h21 #define BT878_VERSION_CODE 0x000000
23 #define BT878_AINT_STAT 0x100
24 #define BT878_ARISCS (0xf<<28)
37 #define BT878_AINT_MASK 0x104
39 #define BT878_AGPIO_DMA_CTL 0x10c
40 #define BT878_A_GAIN (0xf<<28)
47 #define BT878_DA_LRD (0x1f<<16)
52 #define BT878_DA_SDR (0xf<<8)
60 #define BT878_APACK_LEN 0x110
61 #define BT878_AFP_LEN (0xff<<16)
[all …]
/kernel/linux/linux-6.6/drivers/media/pci/bt8xx/
Dbt878.h21 #define BT878_VERSION_CODE 0x000000
23 #define BT878_AINT_STAT 0x100
24 #define BT878_ARISCS (0xf<<28)
37 #define BT878_AINT_MASK 0x104
39 #define BT878_AGPIO_DMA_CTL 0x10c
40 #define BT878_A_GAIN (0xf<<28)
47 #define BT878_DA_LRD (0x1f<<16)
52 #define BT878_DA_SDR (0xf<<8)
60 #define BT878_APACK_LEN 0x110
61 #define BT878_AFP_LEN (0xff<<16)
[all …]
/kernel/linux/linux-5.10/arch/mips/pci/
Dpci-vr41xx.h12 #define PCIU_BASE 0x0f000c00UL
13 #define PCIU_SIZE 0x200UL
15 #define PCIMMAW1REG 0x00
16 #define PCIMMAW2REG 0x04
17 #define PCITAW1REG 0x08
18 #define PCITAW2REG 0x0c
19 #define PCIMIOAWREG 0x10
20 #define IBA(addr) ((addr) & 0xff000000U)
21 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
22 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
[all …]
/kernel/linux/linux-6.6/drivers/phy/qualcomm/
Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
Dphy-qcom-qmp-qserdes-ln-shrd-v6.h9 #define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10 #define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11 #define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
[all …]
Dphy-qcom-qmp-qserdes-txrx-v6_20.h9 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
10 #define QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
11 #define QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN 0xac
12 #define QSERDES_V6_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V6_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V6_20_TX_LANE_MODE_3 0x80
16 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2 0x08
17 #define QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3 0x0c
18 #define QSERDES_V6_20_RX_UCDR_PI_CONTROLS 0x20
19 #define QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3 0x34
[all …]
/kernel/linux/linux-5.10/drivers/phy/qualcomm/
Dphy-qcom-qmp.h10 #define QSERDES_COM_BG_TIMER 0x00c
11 #define QSERDES_COM_SSC_EN_CENTER 0x010
12 #define QSERDES_COM_SSC_ADJ_PER1 0x014
13 #define QSERDES_COM_SSC_ADJ_PER2 0x018
14 #define QSERDES_COM_SSC_PER1 0x01c
15 #define QSERDES_COM_SSC_PER2 0x020
16 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
17 #define QSERDES_COM_SSC_STEP_SIZE2 0x028
18 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
19 #define QSERDES_COM_CLK_ENABLE1 0x038
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/falcon/
Dv1.c38 reg = start | BIT(24) | (secure ? BIT(28) : 0); in nvkm_falcon_v1_load_imem()
39 nvkm_falcon_wr32(falcon, 0x180 + (port * 16), reg); in nvkm_falcon_v1_load_imem()
40 for (i = 0; i < size / 4; i++) { in nvkm_falcon_v1_load_imem()
42 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
43 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
44 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), ((u32 *)data)[i]); in nvkm_falcon_v1_load_imem()
55 if ((i & 0x3f) == 0) in nvkm_falcon_v1_load_imem()
56 nvkm_falcon_wr32(falcon, 0x188 + (port * 16), tag++); in nvkm_falcon_v1_load_imem()
57 nvkm_falcon_wr32(falcon, 0x184 + (port * 16), in nvkm_falcon_v1_load_imem()
62 /* code must be padded to 0x40 words */ in nvkm_falcon_v1_load_imem()
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-orion5x/
Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-orion5x/
Dbridge-regs.h14 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
16 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
18 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
19 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
21 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
23 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
25 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
27 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
29 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
31 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dregs-clock-s3c64xx.h20 #define S3C_PCLK_GATE S3C_CLKREG(0x34)
21 #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
22 #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
31 #define MEM_SYS_CFG_INDEP_CF 0x4000
32 #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
/kernel/linux/linux-6.6/arch/arm/mach-s3c/
Dregs-clock-s3c64xx.h20 #define S3C_PCLK_GATE S3C_CLKREG(0x34)
21 #define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
22 #define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
31 #define MEM_SYS_CFG_INDEP_CF 0x4000
32 #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/
Dpipeline.json4 "EventCode": "0x108",
10 "EventCode": "0x109",
16 "EventCode": "0x10a",
22 "EventCode": "0x10b",
28 "EventCode": "0x10c",
34 "EventCode": "0x10d",
40 "EventCode": "0x10e",
46 "EventCode": "0x10f",
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/ampere/emag/
Dpipeline.json4 "EventCode": "0x108",
10 "EventCode": "0x109",
16 "EventCode": "0x10a",
22 "EventCode": "0x10b",
28 "EventCode": "0x10c",
34 "EventCode": "0x10d",
40 "EventCode": "0x10e",
46 "EventCode": "0x10f",
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/
Dzte,tdm.txt23 reg = <0x01487000 0x1000>;
28 pinctrl-0 = <&tdm_global_pin>;
29 zte,tdm-dma-sysctrl = <&sysctrl 0x10c 4>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Domap4-mcpdm.dtsi12 /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
13 OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
15 /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
16 OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
18 /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
19 OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
21 /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
22 OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
24 /* 0x4a10010e abe_clks.abe_clks ah26 */
25 OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Domap4-mcpdm.dtsi12 /* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
13 OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
15 /* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
16 OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
18 /* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
19 OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
21 /* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
22 OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
24 /* 0x4a10010e abe_clks.abe_clks ah26 */
25 OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-ahb.yaml39 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */

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