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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/
Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/kernel/linux/linux-6.6/arch/powerpc/boot/dts/
Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dtqm5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dcharon.dts23 #size-cells = <0>;
25 PowerPC,5200@0 {
27 reg = <0>;
30 d-cache-size = <0x4000>; // L1, 16K
31 i-cache-size = <0x4000>; // L1, 16K
32 timebase-frequency = <0>; // from bootloader
33 bus-frequency = <0>; // from bootloader
34 clock-frequency = <0>; // from bootloader
38 memory@0 {
40 reg = <0x00000000 0x08000000>; // 128MB
[all …]
Dlite5200.dts20 #size-cells = <0>;
22 PowerPC,5200@0 {
24 reg = <0>;
27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; // from bootloader
35 memory@0 {
37 reg = <0x00000000 0x04000000>; // 64MB
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/sunplus/
Dsunplus-sp7021.dtsi23 #clock-cells = <0>;
33 ranges = <0 0x9c000000 0x400000>;
38 reg = <0x4 0x28>,
39 <0x200 0x44>,
40 <0x268 0x04>;
47 reg = <0x780 0x80>, <0xa80 0x80>;
54 reg = <0xaf00 0x34>, <0xaf80 0x58>;
62 reg = <0x14 0x3>;
65 reg = <0x18 0x2>;
68 reg = <0x34 0x6>;
[all …]
/kernel/linux/linux-5.10/drivers/scsi/
Ddpti.h66 #define DPT_ORGANIZATION_ID (0x1B) /* For Private Messages */
76 #define EMPTY_QUEUE 0xffffffff
77 #define I2O_INTERRUPT_PENDING_B (0x08)
79 #define PCI_DPT_VENDOR_ID (0x1044) // DPT PCI Vendor ID
80 #define PCI_DPT_DEVICE_ID (0xA501) // DPT PCI I2O Device ID
81 #define PCI_DPT_RAPTOR_DEVICE_ID (0xA511)
102 #define FOREVER (0)
113 #define I2O_SCSI_DEVICE_DSC_MASK 0x00FF
115 #define I2O_DETAIL_STATUS_UNSUPPORTED_FUNCTION 0x000A
117 #define I2O_SCSI_DSC_MASK 0xFF00
[all …]
Dg_NCR5380.c69 #define NCR53C400_mem_base 0x3880
70 #define NCR53C400_host_buffer 0x3900
71 #define NCR53C400_region_size 0x3a00
73 #define BOARD_NCR5380 0
92 module_param_hw(ncr_irq, int, irq, 0);
93 module_param_hw(ncr_addr, int, ioport, 0);
94 module_param(ncr_5380, int, 0);
95 module_param(ncr_53c400, int, 0);
96 module_param(ncr_53c400a, int, 0);
97 module_param(dtc_3181e, int, 0);
[all …]
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/i2c/
Dov2722.h38 #define I2C_MSG_LENGTH 0x2
50 * bits 31-16: numerator, bits 15-0: denominator
52 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
56 * bits 31-16: numerator, bits 15-0: denominator
58 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
65 * bits 7-0: min f-number denominator
67 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
68 #define OV2720_ID 0x2720
69 #define OV2722_ID 0x2722
71 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/i2c/
Dov2722.h38 #define I2C_MSG_LENGTH 0x2
47 * bits 31-16: numerator, bits 15-0: denominator
49 #define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064
53 * bits 31-16: numerator, bits 15-0: denominator
55 #define OV2722_F_NUMBER_DEFAULT 0x1a000a
62 * bits 7-0: min f-number denominator
64 #define OV2722_F_NUMBER_RANGE 0x1a0a1a0a
65 #define OV2720_ID 0x2720
66 #define OV2722_ID 0x2722
68 #define OV2722_FINE_INTG_TIME_MIN 0
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/amd/
Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/meson/
Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/meson/
Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/kernel/linux/linux-5.10/include/soc/fsl/qe/
Dimmap_qe.h25 u8 res0[0x04];
27 u8 res1[0x70];
43 u8 res0[0x4];
46 u8 res1[0x4];
48 u8 res2[0x20];
50 u8 res3[0x1C];
58 u8 res0[0xA];
60 u8 res1[0x2];
65 u8 res2[0x8];
69 u8 res3[0x2];
[all …]
/kernel/linux/linux-6.6/include/soc/fsl/qe/
Dimmap_qe.h26 u8 res0[0x04];
28 u8 res1[0x70];
44 u8 res0[0x4];
47 u8 res1[0x4];
49 u8 res2[0x20];
51 u8 res3[0x1C];
59 u8 res0[0xA];
61 u8 res1[0x2];
66 u8 res2[0x8];
70 u8 res3[0x2];
[all …]
/kernel/linux/linux-6.6/drivers/scsi/
Dg_NCR5380.c69 #define NCR53C400_mem_base 0x3880
70 #define NCR53C400_host_buffer 0x3900
71 #define NCR53C400_region_size 0x3a00
73 #define BOARD_NCR5380 0
92 module_param_hw(ncr_irq, int, irq, 0);
93 module_param_hw(ncr_addr, int, ioport, 0);
94 module_param(ncr_5380, int, 0);
95 module_param(ncr_53c400, int, 0);
96 module_param(ncr_53c400a, int, 0);
97 module_param(dtc_3181e, int, 0);
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/exynos/
Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
100 reg = <0x1>;
106 reg = <0x2>;
112 reg = <0x3>;
118 reg = <0x100>;
124 reg = <0x101>;
130 reg = <0x102>;
[all …]
/kernel/linux/linux-6.6/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]

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