| /kernel/linux/linux-6.6/Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
31 6.2.1 One/Three finger touch
33 7. Hardware version 4
36 7.2.1 Status packet
[all …]
|
| /kernel/linux/linux-5.10/Documentation/input/devices/ |
| D | elantech.rst | 4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
6 Extra information for hardware version 1 found and
15 1. Introduction
18 4. Hardware version 1
20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
25 5.2.1 Parity checking and packet re-synchronization
31 6.2.1 One/Three finger touch
33 7. Hardware version 4
36 7.2.1 Status packet
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/sfc/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
54 /* The current version of the MCDI protocol.
[all …]
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/sfc/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
54 /* The current version of the MCDI protocol.
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/icelake/ |
| D | pipeline.json | 4 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
10 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event"
15 …rsion of INST_RETIRED that allows for a more unbiased distribution of samples across instructions …
21 …"BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP …
25 …"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. Th…
35 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
45 …of times the load operation got the true Block-on-Store blocking code preventing store forwarding.…
47 "Counter": "0,1,2,3",
49 "PEBScounters": "0,1,2,3",
56 …"PublicDescription": "Counts the number of times that split load operations are temporarily blocke…
[all …]
|
| D | frontend.json | 4 …"PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from t…
6 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
15 …"PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to th…
17 "Counter": "0,1,2,3",
19 "PEBScounters": "0,1,2,3",
22 "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
27 …"PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Qu…
29 "Counter": "0,1,2,3",
31 "PEBScounters": "0,1,2,3",
[all …]
|
| D | memory.json | 4 "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
6 "Counter": "0,1,2,3",
8 "PEBScounters": "0,1,2,3",
11 …"BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on …
17 "Counter": "0,1,2,3",
19 "PEBScounters": "0,1,2,3",
26 …"PublicDescription": "Counts the number of times a TSX Abort was triggered due to a non-release/co…
28 "Counter": "0,1,2,3",
30 "PEBScounters": "0,1,2,3",
33 …"BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE pref…
[all …]
|
| /kernel/liteos_m/testsuites/sample/kernel/mem/ |
| D | It_los_mem_036.c | 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
12 * of conditions and the following disclaimer in the documentation and/or other materials
15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
[all …]
|
| /kernel/linux/linux-6.6/drivers/net/ethernet/sfc/siena/ |
| D | mcdi_pcol.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
14 #define MC_FW_STATE_POR (1)
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
54 /* The current version of the MCDI protocol.
[all …]
|
| /kernel/linux/linux-5.10/include/uapi/drm/ |
| D | drm_fourcc.h | 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylake/ |
| D | pipeline.json | 3 …of instructions retired from execution. For instructions that consist of multiple micro-ops, Count…
12 …"PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. Th…
13 "Counter": "Fixed counter 1",
18 "CounterHTOff": "Fixed counter 1"
21 "Counter": "Fixed counter 1",
23 "AnyThread": "1",
27 "CounterHTOff": "Fixed counter 1"
30 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
39 …-on-Store blocking code preventing store forwarding. This includes cases when:a. preceding store c…
41 "Counter": "0,1,2,3",
[all …]
|
| /kernel/linux/linux-6.6/include/uapi/drm/ |
| D | drm_fourcc.h | 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
8 * and/or sell copies of the Software, and to permit persons to whom the
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswell/ |
| D | virtual-memory.json | 3 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
5 "Counter": "0,1,2,3",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
13 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
15 "Counter": "0,1,2,3",
19 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
23 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
25 "Counter": "0,1,2,3",
29 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/haswellx/ |
| D | virtual-memory.json | 6 "Counter": "0,1,2,3",
8 "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
15 …oad Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
16 "Counter": "0,1,2,3",
18 …"PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in …
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
25 … Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
26 "Counter": "0,1,2,3",
28 …"PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks …
[all …]
|
| D | pipeline.json | 8 …of instructions retired from execution. For instructions that consist of multiple micro-ops, this …
15 "Counter": "Fixed counter 1",
17 …"PublicDescription": "This event counts the number of thread cycles while the thread is not in a h…
19 "CounterHTOff": "Fixed counter 1"
24 "Counter": "Fixed counter 1",
26 "AnyThread": "1",
28 "CounterHTOff": "Fixed counter 1"
35 …"PublicDescription": "This event counts the number of reference cycles when the core is not in a h…
43 "Counter": "0,1,2,3",
47 "CounterHTOff": "0,1,2,3,4,5,6,7"
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | pipeline.json | 3 "BriefDescription": "Number of instructions retired. General Counter - architectural event",
4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
9 …"PublicDescription": "Counts the number of instructions (EOMs) retired. Counting covers macro-fuse…
13 …"BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread…
14 "Counter": "0,1,2,3",
15 "CounterHTOff": "0,1,2,3,4,5,6,7",
16 "CounterMask": "1",
19 "Invert": "1",
25 …"BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was …
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | pipeline.json | 4 "Counter": "0,1,2,3",
5 "CounterHTOff": "0,1,2,3,4,5,6,7",
9 "PEBS": "1",
16 "Counter": "0,1,2,3",
17 "CounterHTOff": "0,1,2,3,4,5,6,7",
18 "CounterMask": "4",
25 …r of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g…
26 "Counter": "0,1,2,3",
27 "CounterHTOff": "0,1,2,3,4,5,6,7",
35 "Counter": "0,1,2,3",
[all …]
|
| /kernel/linux/linux-6.6/arch/xtensa/variants/dc233c/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2010 Tensilica Inc.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
17 distribute, sublicense, and/or sell copies of the Software, and to
22 in all copies or substantial portions of the Software.
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
[all …]
|
| /kernel/linux/linux-5.10/arch/xtensa/variants/dc233c/include/variant/ |
| D | tie.h | 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
11 Copyright (c) 1999-2010 Tensilica Inc.
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
17 distribute, sublicense, and/or sell copies of the Software, and to
22 in all copies or substantial portions of the Software.
24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
[all …]
|
| /kernel/linux/linux-5.10/arch/alpha/lib/ |
| D | ev6-memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
5 * This is an efficient (and relatively small) implementation of the C library
6 * "memset()" function for the 21264 implementation of Alpha.
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
10 * Much of the information about 21264 scheduling/coding comes from:
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
[all …]
|
| /kernel/linux/linux-6.6/arch/alpha/lib/ |
| D | ev6-memset.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
5 * This is an efficient (and relatively small) implementation of the C library
6 * "memset()" function for the 21264 implementation of Alpha.
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
10 * Much of the information about 21264 scheduling/coding comes from:
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
12 register. The second is the address and length of CPLD register for
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
[all …]
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
12 register. The second is the address and length of CPLD register for
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwell/ |
| D | pipeline.json | 3 …of instructions retired from execution. For instructions that consist of multiple micro-ops, this …
12 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal…
13 "Counter": "Fixed counter 1",
18 "CounterHTOff": "Fixed counter 1"
21 "Counter": "Fixed counter 1",
23 "AnyThread": "1",
27 "CounterHTOff": "Fixed counter 1"
30 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
39 …-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store…
41 "Counter": "0,1,2,3",
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/broadwellx/ |
| D | pipeline.json | 7 …of instructions retired from execution. For instructions that consist of multiple micro-ops, this …
14 "Counter": "Fixed counter 1",
16 …"PublicDescription": "This event counts the number of core cycles while the thread is not in a hal…
18 "CounterHTOff": "Fixed counter 1"
23 "Counter": "Fixed counter 1",
25 "AnyThread": "1",
27 "CounterHTOff": "Fixed counter 1"
34 …of reference cycles when the core is not in a halt state. The core enters the halt state when it i…
41 …"BriefDescription": "Cases when loads get true Block-on-Store blocking code preventing store forwa…
42 "Counter": "0,1,2,3",
[all …]
|