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/kernel/linux/linux-6.6/arch/arm64/crypto/
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
19 ld1 {v0.16b}, [x0] /* load mac */
20 cbz w3, 1f
23 0: ldrb w7, [x1], #1 /* get 1 byte of input */
24 subs w2, w2, #1
25 add w3, w3, #1
27 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
[all …]
Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
25 aese v0.16b, v3.16b
26 aesmc v0.16b, v0.16b
29 aese v0.16b, v1.16b
30 aesmc v0.16b, v0.16b
[all …]
Dsm4-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * https://tools.ietf.org/id/draft-ribose-cfrg-sm4-10.html
13 #include "sm4-ce-asm.h"
15 .arch armv8-a+crypto
17 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
45 * x0: 128-bit key
51 ld1 {v0.16b}, [x0];
52 rev32 v0.16b, v0.16b;
55 ld1 {v24.16b-v27.16b}, [x4], #64;
56 ld1 {v28.16b-v31.16b}, [x4];
[all …]
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
Dsm4-ce-gcm-core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * SM4-GCM AEAD Algorithm using ARMv8 Crypto Extensions
14 #include "sm4-ce-asm.h"
16 .arch armv8-a+crypto
18 .irp b, 0, 1, 2, 3, 24, 25, 26, 27, 28, 29, 30, 31
37 * output: r0:r1 (low 128-bits in r0, high in r1)
41 pmull r0.1q, m0.1d, m1.1d; \
42 pmull T1.1q, m0.1d, T0.1d; \
43 pmull2 T0.1q, m0.2d, T0.2d; \
44 pmull2 r1.1q, m0.2d, m1.2d; \
[all …]
/kernel/linux/linux-5.10/arch/arm64/crypto/
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
20 ld1 {v0.16b}, [x0] /* load mac */
21 cbz w8, 1f
24 0: ldrb w7, [x1], #1 /* get 1 byte of input */
25 subs w2, w2, #1
26 add w8, w8, #1
28 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
[all …]
Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
25 aese v0.16b, v3.16b
26 aesmc v0.16b, v0.16b
29 aese v0.16b, v1.16b
30 aesmc v0.16b, v0.16b
[all …]
Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
55 stp x29, x30, [sp, #-16]!
63 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
[all …]
/kernel/linux/linux-5.10/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h6 * Copyright (C) 2005-2008 Cavium Networks, Inc
14 #define CP0_DCACHE_ERR_REG $27, 1
25 # a2 = 1 if init core, zero otherwise
30 dmfc0 v0, CP0_CVMMEMCTL_REG
32 dins v0, $0, 0, 6
33 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
34 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
35 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
38 or v0, v0, 0x5001
39 xor v0, v0, 0x1001
[all …]
/kernel/linux/linux-6.6/arch/mips/include/asm/mach-cavium-octeon/
Dkernel-entry-init.h6 * Copyright (C) 2005-2008 Cavium Networks, Inc
14 #define CP0_DCACHE_ERR_REG $27, 1
25 # a2 = 1 if init core, zero otherwise
30 dmfc0 v0, CP0_CVMMEMCTL_REG
32 dins v0, $0, 0, 6
33 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
34 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
35 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
38 or v0, v0, 0x5001
39 xor v0, v0, 0x1001
[all …]
/kernel/linux/linux-6.6/tools/testing/selftests/powerpc/math/
Dvmx_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # Should be safe from C, only touches r4, r5 and v0,v1,v2
13 li r3,1 # assume a bad result
15 lvx v0,r5,r4
16 vcmpequd. v1,v0,v20
20 lvx v0,r5,r4
21 vcmpequd. v1,v0,v21
25 lvx v0,r5,r4
26 vcmpequd. v1,v0,v22
30 lvx v0,r5,r4
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/powerpc/math/
Dvmx_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # Should be safe from C, only touches r4, r5 and v0,v1,v2
13 li r3,1 # assume a bad result
15 lvx v0,r5,r4
16 vcmpequd. v1,v0,v20
20 lvx v0,r5,r4
21 vcmpequd. v1,v0,v21
25 lvx v0,r5,r4
26 vcmpequd. v1,v0,v22
30 lvx v0,r5,r4
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdkfd/
Dcwsr_trap_handler_gfx10.asm26 * cpp -DASIC_FAMILY=CHIP_NAVI10 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3
27 * sp3 nv1x.sp3 -hex nv1x.hex
30 * cpp -DASIC_FAMILY=CHIP_SIENNA_CICHLID cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3
31 * sp3 gfx10.sp3 -hex gfx10.hex
34 * cpp -DASIC_FAMILY=CHIP_PLUM_BONITO cwsr_trap_handler_gfx10.asm -P -o gfx11.sp3
35 * sp3 gfx11.sp3 -hex gfx11.hex
48 var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX r…
61 var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1
221 // Let second-level handle non-SAVECTX exception or trap.
222 // Any concurrent SAVECTX will be handled upon re-entry once halted.
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdkfd/
Dcwsr_trap_handler_gfx10.asm26 * cpp -DASIC_TARGET_NAVI1X=1 cwsr_trap_handler_gfx10.asm -P -o nv1x.sp3
27 * sp3-nv1x nv1x.sp3 -hex nv1x.hex
30 * cpp -DASIC_TARGET_NAVI1X=0 cwsr_trap_handler_gfx10.asm -P -o gfx10.sp3
31 * sp3-gfx10 gfx10.sp3 -hex gfx10.hex
36 var SINGLE_STEP_MISSED_WORKAROUND = 1 //workaround for lost MODE.DEBUG_EN exception when SAVECTX r…
52 var SQ_WAVE_IB_STS2_WAVE64_SIZE = 1
70 var SQ_WAVE_IB_STS_REPLAY_W64H_SIZE = 1
72 var SQ_WAVE_IB_STS_FIRST_REPLAY_SIZE = 1
190 // Second-level trap already handled exception if STATUS.HALT=1.
194 // Second-level trap will halt wave and RFE, re-entering for SAVECTX.
[all …]
/kernel/linux/linux-6.6/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
[all …]
/kernel/linux/linux-5.10/arch/powerpc/crypto/
Dcrc32-vpmsum_core.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dctrl.c38 struct nvif_control_pstate_info_v0 v0; in nvkm_control_mthd_pstate_info() member
40 struct nvkm_clk *clk = ctrl->device->clk; in nvkm_control_mthd_pstate_info()
41 int ret = -ENOSYS; in nvkm_control_mthd_pstate_info()
43 nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size); in nvkm_control_mthd_pstate_info()
44 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in nvkm_control_mthd_pstate_info()
45 nvif_ioctl(&ctrl->object, "control pstate info vers %d\n", in nvkm_control_mthd_pstate_info()
46 args->v0.version); in nvkm_control_mthd_pstate_info()
51 args->v0.count = clk->state_nr; in nvkm_control_mthd_pstate_info()
52 args->v0.ustate_ac = clk->ustate_ac; in nvkm_control_mthd_pstate_info()
53 args->v0.ustate_dc = clk->ustate_dc; in nvkm_control_mthd_pstate_info()
[all …]
Duser.c51 return -EINVAL; in nvkm_udevice_info_subdev()
57 return -ENODEV; in nvkm_udevice_info_subdev()
64 if (args->mthd & NV_DEVICE_INFO_UNIT) { in nvkm_udevice_info_v1()
65 if (nvkm_udevice_info_subdev(device, args->mthd, &args->data)) in nvkm_udevice_info_v1()
66 args->mthd = NV_DEVICE_INFO_INVALID; in nvkm_udevice_info_v1()
69 args->mthd = NV_DEVICE_INFO_INVALID; in nvkm_udevice_info_v1()
75 struct nvkm_object *object = &udev->object; in nvkm_udevice_info()
76 struct nvkm_device *device = udev->device; in nvkm_udevice_info()
77 struct nvkm_fb *fb = device->fb; in nvkm_udevice_info()
78 struct nvkm_instmem *imem = device->imem; in nvkm_udevice_info()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dctrl.c38 struct nvif_control_pstate_info_v0 v0; in nvkm_control_mthd_pstate_info() member
40 struct nvkm_clk *clk = ctrl->device->clk; in nvkm_control_mthd_pstate_info()
41 int ret = -ENOSYS; in nvkm_control_mthd_pstate_info()
43 nvif_ioctl(&ctrl->object, "control pstate info size %d\n", size); in nvkm_control_mthd_pstate_info()
44 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in nvkm_control_mthd_pstate_info()
45 nvif_ioctl(&ctrl->object, "control pstate info vers %d\n", in nvkm_control_mthd_pstate_info()
46 args->v0.version); in nvkm_control_mthd_pstate_info()
51 args->v0.count = clk->state_nr; in nvkm_control_mthd_pstate_info()
52 args->v0.ustate_ac = clk->ustate_ac; in nvkm_control_mthd_pstate_info()
53 args->v0.ustate_dc = clk->ustate_dc; in nvkm_control_mthd_pstate_info()
[all …]
Duser.c51 return -EINVAL; in nvkm_udevice_info_subdev()
57 return -ENODEV; in nvkm_udevice_info_subdev()
64 if (args->mthd & NV_DEVICE_INFO_UNIT) { in nvkm_udevice_info_v1()
65 if (nvkm_udevice_info_subdev(device, args->mthd, &args->data)) in nvkm_udevice_info_v1()
66 args->mthd = NV_DEVICE_INFO_INVALID; in nvkm_udevice_info_v1()
70 switch (args->mthd) { in nvkm_udevice_info_v1()
72 for (_i = (B), args->data = 0ULL; _i <= (C); _i++) { \ in nvkm_udevice_info_v1()
74 args->data |= BIT_ULL(_i); \ in nvkm_udevice_info_v1()
97 args->mthd = NV_DEVICE_INFO_INVALID; in nvkm_udevice_info_v1()
105 struct nvkm_object *object = &udev->object; in nvkm_udevice_info()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/core/
Dioctl.c37 struct nvif_ioctl_nop_v0 v0; in nvkm_ioctl_nop() member
39 int ret = -ENOSYS; in nvkm_ioctl_nop()
42 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in nvkm_ioctl_nop()
43 nvif_ioctl(object, "nop vers %lld\n", args->v0.version); in nvkm_ioctl_nop()
44 args->v0.version = NVIF_VERSION_LATEST; in nvkm_ioctl_nop()
55 if ( object->func->uevent && in nvkm_ioctl_sclass_()
56 !object->func->uevent(object, NULL, 0, NULL) && index-- == 0) { in nvkm_ioctl_sclass_()
57 oclass->ctor = nvkm_uevent_new; in nvkm_ioctl_sclass_()
58 oclass->base.minver = 0; in nvkm_ioctl_sclass_()
59 oclass->base.maxver = 0; in nvkm_ioctl_sclass_()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/core/
Dioctl.c36 struct nvif_ioctl_nop_v0 v0; in nvkm_ioctl_nop() member
38 int ret = -ENOSYS; in nvkm_ioctl_nop()
41 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) { in nvkm_ioctl_nop()
42 nvif_ioctl(object, "nop vers %lld\n", args->v0.version); in nvkm_ioctl_nop()
43 args->v0.version = NVIF_VERSION_LATEST; in nvkm_ioctl_nop()
54 struct nvif_ioctl_sclass_v0 v0; in nvkm_ioctl_sclass() member
57 int ret = -ENOSYS, i = 0; in nvkm_ioctl_sclass()
60 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { in nvkm_ioctl_sclass()
62 args->v0.version, args->v0.count); in nvkm_ioctl_sclass()
63 if (size != args->v0.count * sizeof(args->v0.oclass[0])) in nvkm_ioctl_sclass()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Drootnv50.c40 struct nv50_disp_mthd_v0 v0; in nv50_disp_root_mthd_() member
44 struct nv50_disp *disp = root->disp; in nv50_disp_root_mthd_()
48 int hidx, ret = -ENOSYS; in nv50_disp_root_mthd_()
51 return -EINVAL; in nv50_disp_root_mthd_()
54 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, true))) { in nv50_disp_root_mthd_()
56 args->v0.version, args->v0.method, args->v0.head); in nv50_disp_root_mthd_()
57 mthd = args->v0.method; in nv50_disp_root_mthd_()
58 hidx = args->v0.head; in nv50_disp_root_mthd_()
60 if (!(ret = nvif_unpack(ret, &data, &size, args->v1, 1, 1, true))) { in nv50_disp_root_mthd_()
63 args->v1.version, args->v1.method, in nv50_disp_root_mthd_()
[all …]
/kernel/linux/linux-6.6/lib/
Dsiphash.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 /* Copyright (C) 2016-2022 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
4 * SipHash: a fast short-input PRF
7 * This implementation is specifically for SipHash2-4 for a secure PRF
8 * and HalfSipHash1-3/SipHash1-3 for an insecure PRF only suitable for
17 #include <asm/word-at-a-time.h>
20 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
23 u64 v0 = SIPHASH_CONST_0; \
28 v3 ^= key->key[1]; \
29 v2 ^= key->key[0]; \
[all …]
/kernel/linux/linux-5.10/lib/
Dsiphash.c5 * SipHash: a fast short-input PRF
8 * This implementation is specifically for SipHash2-4 for a secure PRF
9 * and HalfSipHash1-3/SipHash1-3 for an insecure PRF only suitable for
18 #include <asm/word-at-a-time.h>
21 #define SIPROUND SIPHASH_PERMUTATION(v0, v1, v2, v3)
24 u64 v0 = SIPHASH_CONST_0; \
29 v3 ^= key->key[1]; \
30 v2 ^= key->key[0]; \
31 v1 ^= key->key[1]; \
32 v0 ^= key->key[0];
[all …]

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