Searched +full:4 +full:- +full:cpu (Results 1 – 25 of 1104) sorted by relevance
12345678910>>...45
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| D | hip06.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/hisilicon/ |
| D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| D | hip06.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | cpu_hotplug.rst | 2 CPU hotplug in the Kernel
18 insertion and removal require support for CPU hotplug.
21 provisioning reasons, or for RAS purposes to keep an offending CPU off
22 system execution path. Hence the need for CPU hotplug support in the
25 A more novel use of CPU-hotplug support is its use today in suspend resume
26 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
58 CPU maps
71 after a CPU is available for kernel scheduling and ready to receive
72 interrupts from devices. Its cleared when a CPU is brought down using
74 migrated to another target CPU.
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/kernel/ |
| D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
27 * may prevent a CPU from being onlined at all.
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
[all …]
|
| /kernel/linux/linux-6.6/Documentation/translations/zh_CN/core-api/ |
| D | cpu_hotplug.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/cpu_hotplug.rst
85 hot-add/hot-remove。目前还没有定死规定。典型的用法是在启动时启动拓扑结构，这时
101 $ ls -lh /sys/devices/system/cpu
103 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu0
104 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu1
105 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu2
106 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu3
107 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu4
108 drwxr-xr-x 9 root root 0 Dec 21 16:33 cpu5
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/hisilicon/ |
| D | hip04.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
|
| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | hip04.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 Hisilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
|
| D | highbank.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@900 {
22 compatible = "arm,cortex-a9";
[all …]
|
| D | ecx-2000.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
|
| /kernel/linux/linux-6.6/Documentation/core-api/ |
| D | cpu_hotplug.rst | 2 CPU hotplug in the Kernel
19 insertion and removal require support for CPU hotplug.
22 provisioning reasons, or for RAS purposes to keep an offending CPU off
23 system execution path. Hence the need for CPU hotplug support in the
26 A more novel use of CPU-hotplug support is its use today in suspend resume
27 support for SMP. Dual-core and HT support makes even a laptop run SMP kernels
59 CPU maps
72 after a CPU is available for kernel scheduling and ready to receive
73 interrupts from devices. Its cleared when a CPU is brought down using
75 migrated to another target CPU.
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/cavium/ |
| D | thunder-88xx.dtsi | 2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/cavium/ |
| D | thunder-88xx.dtsi | 2 * Cavium Thunder DTS file - Thunder SoC description
6 * This file is dual-licensed: you can use it either under the terms
24 * MA 02110-1301 USA
51 compatible = "cavium,thunder-88xx";
52 interrupt-parent = <&gic0>;
53 #address-cells = <2>;
54 #size-cells = <2>;
57 compatible = "arm,psci-0.2";
62 #address-cells = <2>;
63 #size-cells = <0>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
[all …]
|
| /kernel/linux/linux-6.6/arch/arm64/kernel/ |
| D | cpufeature.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Contains CPU feature definitions
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
17 * CPU when bringing them up. If there is a mismatch, then we update the
18 * snapshot state to indicate the lowest-common denominator of the feature,
27 * may prevent a CPU from being onlined at all.
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
[all …]
|
| /kernel/linux/build/test/moduletest/runtest/bin/cpuisolation_t/testcases/bin/ |
| D | cpuisolation01.sh | 5 # SPDX-License-Identifier: GPL-2.0
16 # Description: check rw nodes test about CPU lightweight isolation
18 # Authors: liudanning - liudanning@h-partners.com
20 # History: Mar 24 2022 - init scripts
28 echo 0 > /sys/devices/system/cpu/cpu0/core_ctl/min_cpus
29 echo 4 > /sys/devices/system/cpu/cpu0/core_ctl/max_cpus
51 if [ $mode -eq 1 ]; then
52 if [ $ret_min -eq 1 ]; then
54 elif [ $min_cpus_value -eq 4 ]; then
56 elif [ $ret_max -eq 1 ]; then
[all …]
|
| /kernel/linux/linux-5.10/include/linux/irqchip/ |
| D | irq-bcm2836.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
33 * The CPU's interrupt status register. Bits are defined by the
[all …]
|
| /kernel/linux/linux-6.6/include/linux/irqchip/ |
| D | irq-bcm2836.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13 * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21 * The low 4 bits of this are the CPU's timer IRQ enables, and the
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
27 * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
33 * The CPU's interrupt status register. Bits are defined by the
[all …]
|
| /kernel/linux/linux-6.6/arch/arm/boot/dts/calxeda/ |
| D | highbank.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
21 cpu@900 {
22 compatible = "arm,cortex-a9";
[all …]
|
| D | ecx-2000.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
6 /dts-v1/;
8 /* First 4KB has pen for secondary cores. */
12 model = "Calxeda ECX-2000";
13 compatible = "calxeda,ecx-2000";
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
[all …]
|
| /kernel/linux/linux-5.10/arch/mips/netlogic/xlr/ |
| D | fmn-config.c | 2 * Copyright (c) 2003-2012 Broadcom Corporation
35 #include <asm/cpu-info.h>
39 #include <asm/cpu.h>
60 xlr_board_fmn_config.bucket_size[(bkt * 8) + 4], in print_credit_config()
70 fmn_info->credit_config[(bkt * 8) + 0], in print_credit_config()
71 fmn_info->credit_config[(bkt * 8) + 1], in print_credit_config()
72 fmn_info->credit_config[(bkt * 8) + 2], in print_credit_config()
73 fmn_info->credit_config[(bkt * 8) + 3], in print_credit_config()
74 fmn_info->credit_config[(bkt * 8) + 4], in print_credit_config()
75 fmn_info->credit_config[(bkt * 8) + 5], in print_credit_config()
[all …]
|
| /kernel/linux/linux-6.6/Documentation/admin-guide/ |
| D | cputopology.rst | 2 How CPU topology info is exported via sysfs
5 CPU topology info is exported via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/. Please refer to the ABI file:
8 Documentation/ABI/stable/sysfs-devices-system-cpu.
10 Architecture-neutral, drivers/base/topology.c, exports these attributes.
16 these macros in include/asm-XXX/topology.h::
18 #define topology_physical_package_id(cpu)
19 #define topology_die_id(cpu)
20 #define topology_cluster_id(cpu)
21 #define topology_core_id(cpu)
[all …]
|
| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 device_type = "cpu";
[all …]
|
12345678910>>...45