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Searched +full:cortex +full:- +full:m (Results 1 – 25 of 181) sorted by relevance

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/kernel/liteos_m/arch/arm/cortex-m55/gcc/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2022-2023 Huawei Device Co., Ltd. All rights reserved. 66 * Count of M-Core system interrupt vector. 72 * Count of M-Core interrupt vector. 83 …* The value range of the interrupt number applicable for a Cortex-M55 platformis [OS_USER_HWI_MIN… 93 * Solution: Pass in a valid non-null hardware interrupt handling function. 123 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 134 * The value range of the interrupt priority applicable for a Cortex-M55 platform is [0,15]. 155 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 183 * Interrupt Priority-Level Registers. 189 * Interrupt enable register for 0-31. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m3/keil/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 63 * Count of M-Core system interrupt vector. 69 * Count of M-Core interrupt vector. 92 …* The value range of the interrupt number applicable for a Cortex-M3 platform is [OS_USER_HWI_MIN,… 102 * Solution: Pass in a valid non-null hardware interrupt handling function. 132 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 143 * The value range of the interrupt priority applicable for a Cortex-M3 platform is [0,15]. 164 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 192 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m4/iar/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M4 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m4/gcc/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m7/gcc/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 61 * Count of M-Core system interrupt vector. 67 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M7 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M7 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m55/gcc/TZ/non_secure/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m7/iar/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M7 platformis [OS_USER_HWI_MIN,… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M7 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/gcc/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m55/iar/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/arch/arm/cortex-m33/iar/NTZ/
D	los_arch_interrupt.h	2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. 73 * Count of M-Core system interrupt vector. 79 * Count of M-Core interrupt vector. 90 …* The value range of the interrupt number applicable for a Cortex-M33 platform is [OS_USER_HWI_MI… 100 * Solution: Pass in a valid non-null hardware interrupt handling function. 130 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 141 * The value range of the interrupt priority applicable for a Cortex-M33 platform is [0,15]. 162 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be… 190 * Interrupt Priority-Level Registers. [all …]
/kernel/liteos_m/
D	README.md	1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a> 3 - [Introduction](#section11660541593) 4 - [Directory Structure](#section161941989596) 5 - [Constraints](#section119744591305) 6 - [Usage](#section3732185231214) 7 - [Contribution](#section1371123476307) 8 - [Repositories Involved](#section1371113476307) 12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe… 13 Figure1 shows the architecture of the LiteOS-M kernel. 15 Figure 1 Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a> [all …]
/kernel/liteos_m/arch/arm/
D	Kconfig	4 # ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations 10 32-bit ARM architecture implementations, Except the M-profile. 11 It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc. 27 default "armv7-m" if ARCH_ARM_V7M 28 default "armv8-m" if ARCH_ARM_V8M 48 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles. 49 …VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support co… 54 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles. 55 …VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support co… 56 …VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to … [all …]
/kernel/linux/linux-6.6/arch/arm/mm/
D	proc-v7m.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm/mm/proc-v7m.S 8 * This is the "shell" of the ARMv7-M processor support. 14 #include "proc-macros.S" 31 * - loc - location to jump to for soft reset 104 * This should be able to cover all ARMv7-M cores. 140 ldmia sp, {r0-r3, r12} 144 @ Special-purpose control register 150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 152 teq r8, #0 @ re-evalutae condition [all …]`
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/
D	arm,corstone1000.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vishnu Banavath <vishnu.banavath@arm.com> 11 - Rui Miguel Silva <rui.silva@linaro.org> 14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that 15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M 18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion 19 systems for M-Class (or other) processors for adding sensors, connectivity, 25 seamless integration of the optional CryptoCell™-312 cryptographic [all …]
D	actions.yaml	`1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andreas Färber <afaerber@suse.de> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC. 19 - items: 20 - enum: 21 - allo,sparky # Allo.com Sparky 22 - cubietech,cubieboard6 # Cubietech CubieBoard6 [all …]`
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/stm32/
D	st,mlahb.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 title: STMicroelectronics STM32 ML-AHB interconnect bindings 10 - Fabien Dessenne <fabien.dessenne@st.com> 11 - Arnaud Pouliquen <arnaud.pouliquen@st.com> 14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory 17 using different buses (see [2]): balancing the Cortex-M firmware accesses 23 - $ref: /schemas/simple-bus.yaml# [all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/arm/stm32/
D	st,mlahb.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 ML-AHB interconnect 10 - Fabien Dessenne <fabien.dessenne@foss.st.com> 11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com> 14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory 17 using different buses (see [2]): balancing the Cortex-M firmware accesses 23 - $ref: /schemas/simple-bus.yaml# [all …]
/kernel/linux/linux-5.10/arch/arm/mm/
D	proc-v7m.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm/mm/proc-v7m.S 8 * This is the "shell" of the ARMv7-M processor support. 14 #include "proc-macros.S" 31 * - loc - location to jump to for soft reset 104 * This should be able to cover all ARMv7-M cores. 140 ldmia sp, {r0-r3, r12} 144 @ Special-purpose control register 150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 152 teq r8, #0 @ re-evalutae condition [all …]`
/kernel/uniproton/
D	uniproton.gni	1 # Copyright (c) 2022-2022 Huawei Technologies Co., Ltd. All rights reserved. 8 # EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11 # Create: 2022-09-21 27 " --header-path $MENUCONFIG_H" + " --file-list kconfig_files.txt" + 28 " --env-list kconfig_env.txt" + " --config-out config.gni" ], 42 cmd = "grep -c '^\s$kernel_module\\|hdf_driver$\s(\s\S\s)\s{\s\$' $build_gn" 48 …cmd = "if grep -q '^\s$config\s(\s\"public\"\s)\\|module_group\s(\s\"\S\"\s)$\s{\s\$' $… 59 …cmd = "if grep -q '^\s$module_group\\|group$\s(\s\"$current_dir_name\"\s)\s{\s*\$' $build_gn… 113 foreach(m, invoker.modules) { 114 deps += [ m ] [all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/
D	actions.yaml	`1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andreas Färber <afaerber@suse.de> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC. 19 - items: 20 - enum: 21 - allo,sparky # Allo.com Sparky 22 - cubietech,cubieboard6 # Cubietech CubieBoard6 [all …]`
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/sound/
D	fsl,rpmsg.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shengjiu Wang <shengjiu.wang@nxp.com> 14 are SAI, MICFIL, DMA controlled by Cortex M core. What we see from 18 Cortex-A and Cortex-M. 21 - $ref: sound-card-common.yaml# 26 - fsl,imx7ulp-rpmsg-audio 27 - fsl,imx8mn-rpmsg-audio 28 - fsl,imx8mm-rpmsg-audio [all …]`
/kernel/linux/linux-6.6/Documentation/translations/zh_TW/arch/arm64/
D	silicon-errata.txt	1 SPDX-License-Identifier: GPL-2.0 3 Chinese translated version of Documentation/arch/arm64/silicon-errata.rst 11 M: Will Deacon <will.deacon@arm.com> 15 --------------------------------------------------------------------- 16 Documentation/arch/arm64/silicon-errata.rst 的中文翻譯 30 --------------------------------------------------------------------- 55 相應的內核配置（Kconfig）選項被加在「內核特性（Kernel Features）」-> 66 +----------------+-----------------+-----------------+-------------------------+ 67 \| ARM \| Cortex-A53 \| #826319 \| ARM64_ERRATUM_826319 \| 68 \| ARM \| Cortex-A53 \| #827319 \| ARM64_ERRATUM_827319 \| [all …]

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