| /kernel/linux/linux-5.10/drivers/fpga/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds a FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
[all …]
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| D | ts73xx-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
44 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
46 /* Reset the FPGA */ in ts73xx_fpga_write_init()
47 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
49 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
58 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write()
[all …]
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| /kernel/linux/linux-6.6/drivers/fpga/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
26 FPGA manager driver support for Altera Arria10 SoCFPGA.
41 tristate "Altera FPGA Passive Serial over SPI"
[all …]
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| D | ts73xx-fpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
53 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/can/ctucanfd/ |
| D | Kconfig | 2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
20 The project providing FPGA design for Intel EP4CGX15 based DB4CGX15
22 at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd .
[all …]
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| /kernel/linux/linux-5.10/Documentation/fpga/ |
| D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
11 The Device Feature List (DFL) FPGA framework (and drivers according to
14 configure, enumerate, open and access FPGA accelerators on platforms which
16 enables system level management functions such as FPGA reconfiguration.
23 walk through these predefined data structures to enumerate FPGA features:
24 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
28 +----------+ +-->+----------+ +-->+----------+ +-->+----------+
[all …]
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| /kernel/linux/linux-5.10/drivers/watchdog/ |
| D | pika_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
[all …]
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| /kernel/linux/linux-6.6/drivers/watchdog/ |
| D | pika_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
[all …]
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| /kernel/linux/linux-5.10/drivers/staging/gs_fpgaboot/ |
| D | README | 2 Linux Driver Source for Xilinx FPGA firmware download
16 - Download Xilinx FPGA firmware
17 - This module downloads Xilinx FPGA firmware using gpio pins.
21 An FPGA (Field Programmable Gate Array) is a programmable hardware that is
24 This driver provides a way to download FPGA firmware.
28 - load Xilinx FPGA bitstream format[1] firmware image file using
30 - program the Xilinx FPGA using SelectMAP (parallel) mode [2]
31 - FPGA prgram is done by gpio based bit-banging, as an example
32 - platform independent file: gs_fpgaboot.c
33 - platform dependent file: io.c
[all …]
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| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
[all …]
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| D | men-chameleon-bus.rst | 30 ----------------------
34 based devices.
37 -----------------------------------------
39 The current implementation is limited to PCI and PCIe based carrier devices
43 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
44 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
46 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
47 per MCB device like PCIe based carriers with MSI or MSI-X support.
54 - The MEN Chameleon Bus itself,
55 - drivers for MCB Carrier Devices and
[all …]
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| /kernel/linux/linux-6.6/Documentation/driver-api/ |
| D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
[all …]
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| D | men-chameleon-bus.rst | 31 ----------------------
35 based devices.
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/ |
| D | ebony.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on earlier code:
9 * Copyright 2002-2005 MontaVista Software Inc.
30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
32 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
38 u8 *fpga; in ebony_flashsel_fixup() local
43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup()
45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup()
46 fatal("%s has missing or invalid virtual-reg property\n\r", in ebony_flashsel_fixup()
49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup()
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/ |
| D | ebony.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on earlier code:
9 * Copyright 2002-2005 MontaVista Software Inc.
30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
32 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
38 u8 *fpga; in ebony_flashsel_fixup() local
43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup()
45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup()
46 fatal("%s has missing or invalid virtual-reg property\n\r", in ebony_flashsel_fixup()
49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup()
[all …]
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| /kernel/linux/linux-5.10/drivers/mcb/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
14 an FPGA and provide the necessary framework for instantiating drivers
21 tristate "PCI based MCB carrier"
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
33 tristate "LPC (non PCI) based MCB carrier"
39 If build as a module, the module is called mcb-lpc.ko
|
| /kernel/linux/linux-6.6/drivers/mcb/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
14 an FPGA and provide the necessary framework for instantiating drivers
21 tristate "PCI based MCB carrier"
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
33 tristate "LPC (non PCI) based MCB carrier"
39 If build as a module, the module is called mcb-lpc.ko
|
| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | fpga-dfl.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
[all …]
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| /kernel/linux/linux-6.6/include/uapi/linux/ |
| D | fpga-dfl.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
[all …]
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| /kernel/linux/linux-6.6/Documentation/fpga/ |
| D | dfl.rst | 2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
[all …]
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| /kernel/linux/linux-6.6/arch/powerpc/boot/dts/fsl/ |
| D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
[all …]
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| /kernel/linux/linux-5.10/drivers/media/pci/cx23885/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
48 This is a video4linux driver for Conexant 23885 based
55 tristate "Altera FPGA based CI module"
59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.
62 module will be called altera-ci
|
| /kernel/linux/linux-6.6/drivers/media/pci/cx23885/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
48 This is a video4linux driver for Conexant 23885 based
55 tristate "Altera FPGA based CI module"
59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.
62 module will be called altera-ci
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | mdio-mux-multiplexer.txt | 5 producer, gpio mux producer or generic register based mux producer.
9 - compatible : should be "mmio-mux-multiplexer"
10 - mux-controls : mux controller node to use for operating the mux
11 - mdio-parent-bus : phandle to the parent MDIO bus.
17 Documentation/devicetree/bindings/mux/mux-controller.txt
18 and Documentation/devicetree/bindings/net/mdio-mux.txt
24 fpga@66 { // fpga connected to i2c
25 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
26 "simple-mfd";
29 mux: mux-controller { // Mux Producer
[all …]
|